mips.h

国产CPU－龙芯（loongson)BIOS源代码

/* $Id: mips.h,v 1.2 2003/07/07 10:14:14 baozheng Exp $ */
/* mips.h - machine dependent definitions for the MIPS architecture
 *	The contents of this file are not copyrighted in any
 *	way, and may therefore be used without restriction.
 */

/*
 * This file supports both the LR3000 and the LR33000. By default
 * the LR3000 is assumed. For the LR33000 invoke the compiler with
 * the option -DLR33000.
 *
 * This file also supports development under SABLE, (the simulator
 * supplied with SPP). To compile for the SABLE environment, invoke
 * the compiler with the option -DSABLE.
 */

#ifndef _MIPS_
#define _MIPS_

#if #system(sde)
# if defined(__ASSEMBLER__) 
#  ifndef LANGUAGE_ASSEMBLY 
#   define LANGUAGE_ASSEMBLY 
#  endif 
# else 
#  ifndef LANGUAGE_C 
#   define LANGUAGE_C 
#  endif 
# endif  
#else 
# ifndef LANGUAGE_C
#  define LANGUAGE_C
# endif
#endif

#define K0BASE 		0x80000000
#define K0SIZE 		0x20000000
#define K1BASE 		0xa0000000
#define K1SIZE 		0x20000000
#define K2BASE 		0xc0000000

#define GEN_VECT 	0x80000080
#define UTLB_VECT 	0x80000000

#ifdef LANGUAGE_ASSEMBLY

#define PHYS_TO_K0(pa)	((pa)|K0BASE)
#define PHYS_TO_K1(pa)	((pa)|K1BASE)
#define K0_TO_PHYS(va)	((va)&(K0SIZE-1))
#define K1_TO_PHYS(va)	((va)&(K1SIZE-1))
#define K0_TO_K1(va)	((va)|K1SIZE)
#define K1_TO_K0(va)	((va)&~K1SIZE)

/* SDE compatibility */
#ifndef KSEG0_BASE
#define PA_TO_KVA0(pa)	PHYS_TO_K0(pa)
#define PA_TO_KVA1(pa)	PHYS_TO_K1(pa)
#define KVA_TO_PA(pa)	K1_TO_PHYS(pa)
#define KSEG0_BASE	K0BASE
#define KSEG1_BASE	K1BASE
#endif

#define jr j
#define jalr jal

/* aliases for general registers */
#define zero		$0
#define	AT		$1		/* assembler temporaries */
#define	v0		$2		/* value holders */
#define	v1		$3
#define	a0		$4		/* arguments */
#define	a1		$5
#define	a2		$6
#define	a3		$7
#define	t0		$8		/* temporaries */
#define	t1		$9
#define	t2		$10
#define	t3		$11
#define	t4		$12
#define	t5		$13
#define	t6		$14
#define	t7		$15
#define ta0		$12
#define ta1		$13
#define ta2		$14
#define ta3		$15
#define	s0		$16		/* saved registers */
#define	s1		$17
#define	s2		$18
#define	s3		$19
#define	s4		$20
#define	s5		$21
#define	s6		$22
#define	s7		$23
#define	t8		$24		/* temporaries */
#define	t9		$25
#define	k0		$26		/* kernel registers */
#define	k1		$27
#define	gp		$28		/* global pointer */
#define	sp		$29		/* stack pointer */
#define	s8		$30		/* saved register */
#define	fp		$30		/* frame pointer (old usage) */
#define	ra		$31		/* return address */

/* System Control Coprocessor (CP0) registers */
#define C0_SR		$12		/* Processor Status */
#define C0_STATUS	$12		/* Processor Status */
#define C0_CAUSE	$13		/* Exception Cause */
#define C0_EPC		$14		/* Exception PC */
#define C0_BADADDR	$8		/* Bad Address */
#define C0_BADVADDR	$8		/* Bad Virtual Address */
#define C0_PRID		$15		/* Processor Revision Indentifier */

#ifdef LR33000
#include "lr33000.h"
#else 
#define C0_CTEXT	$4		/* Context */
#define C0_TLBHI	$10		/* TLB EntryHi */
#define C0_TLBLO	$2		/* TLB EntryLo */
#define C0_INX		$0		/* TLB Index */
#define C0_RAND		$1		/* TLB Random */
#ifdef R4000
#define C0_TLBLO0	$2		/* TLB EntryLo0 */
#define C0_TLBLO1	$3		/* TLB EntryLo1 */
#define C0_PGMASK	$5		/* TLB PageMask */
#define C0_WIRED	$6		/* TLB Wired */
#define C0_COUNT 	$9		/* Count */
#define C0_COMPARE	$11		/* Compare */
#define C0_CONFIG	$16		/* Config */
#define C0_LLADDR	$17		/* LLAddr */
#define C0_WATCHLO	$18		/* WatchpointLo */
#define C0_WATCHHI	$19		/* WatchpointHi */
#define C0_XCTEXT	$20		/* XContext */
#define C0_WATCHMASK	$24		/* RM7000 Watchmask */
#define C0_ECC		$26		/* ECC */
#define C0_CACHEERR	$27		/* CacheErr */
#define C0_TAGLO	$28		/* TagLo */
#define C0_TAGHI	$29		/* TagHi */
#define C0_ERREPC	$30		/* ErrorEPC */

/* RM7000 control registers, access via cfc0/ctc0 */
#define C0C_IPLLO	$18
#define C0C_IPLHI	$19
#define C0C_ICR		$20
#define C0C_DERRADDR1	$26
#define C0C_DERRADDR2	$27
#endif /* R4000 */
#endif /* !LR33000 */

/* Floating-Point Control registers */
#define FPA_CSR		$31		/* Control/Status register */
#define FPA_IRR		$0		/* Implementation/Revision register */

#define LEAF(name) \
  	.text; \
  	.globl	name; \
  	.ent	name; \
name:

#define XLEAF(name) \
  	.text; \
  	.globl	name; \
  	.aent	name; \
name:

#define SLEAF(name) \
  	.text; \
  	.ent	name; \
name:

#define END(name) \
  	.size name,.-name; \
  	.end	name

#define SEND(name) END(name)

#define EXPORT(name) \
  	.globl name; \
name:

#define EXPORTS(name,sz) \
  	.globl name; \
name:

#define	IMPORT(name, size) \
	.extern	name,size

#define BSS(name,size) \
	.comm	name,size

#define LBSS(name,size) \
  	.lcomm	name,size

#else /* LANGUAGE_C */

#define PHYS_TO_K0(pa)	((unsigned)(pa)|K0BASE)
#define PHYS_TO_K1(pa)	((unsigned)(pa)|K1BASE)
#define K0_TO_PHYS(va)	((unsigned)(va)&(K0SIZE-1))
#define K1_TO_PHYS(va)	((unsigned)(va)&(K1SIZE-1))
#define K0_TO_K1(va)	((unsigned)(va)|K1SIZE)
#define K1_TO_K0(va)	((unsigned)(va)&~K1SIZE)

#define	IS_K0SEG(x)	((unsigned)(x) >= K0BASE && (unsigned)(x) < K1BASE)
#define	IS_K1SEG(x)	((unsigned)(x) >= K1BASE && (unsigned)(x) < K2BASE)

/* SDE compatibility */
#ifndef KSEG0_BASE
#define KSEG0_BASE	(void *)K0BASE
#define KSEG1_BASE	(void *)K1BASE
#define PA_TO_KVA0(pa)	(void *)PHYS_TO_K0(pa)
#define PA_TO_KVA1(pa)	(void *)PHYS_TO_K1(pa)
#define KVA_TO_PA(pa)	K1_TO_PHYS(pa)
#define KVA0_TO_KVA1(v)	(void *)K0_TO_K1(v)
#define KVA1_TO_KVA0(v)	(void *)K1_TO_K0(v)
#define IS_KVA(v)	((int)(v) < 0)
#define IS_KVA0(v)	(((unsigned)(v) >> 29) == 0x4)
#define IS_KVA1(v)	(((unsigned)(v) >> 29) == 0x5)
#define IS_KVA01(v)	(((unsigned)(v) >> 30) == 0x2)
#endif /* KSEG0_BASE */

#define C0_SR		12		/* Processor Status */
#define C0_STATUS	12		/* Processor Status */
#define C0_CAUSE	13		/* Exception Cause */
#define C0_EPC		14		/* Exception PC */
#define C0_BADADDR	8		/* Bad Address */
#define C0_BADVADDR	8		/* Bad Virtual Address */
#define C0_PRID		15		/* Processor Revision Indentifier */

#ifdef LR33000
#include "lr33000.h"
#else
#define C0_CTEXT	4		/* Context */
#define C0_TLBHI	10		/* TLB EntryHi */
#define C0_TLBLO	2		/* TLB EntryLo */
#define C0_INX		0		/* TLB Index */
#define C0_RAND		1		/* TLB Random */
#ifdef R4000
#define C0_TLBLO0	2		/* TLB EntryLo0 */
#define C0_TLBLO1	3		/* TLB EntryLo1 */
#define C0_PGMASK	5		/* TLB PageMask */
#define C0_WIRED	6		/* TLB Wired */
#define C0_COUNT 	9		/* Count */
#define C0_COMPARE	11		/* Compare */
#define C0_CONFIG	16		/* Config */
#define C0_LLADDR	17		/* LLAddr */
#define C0_WATCHLO	18		/* WatchpointLo */
#define C0_WATCHHI	19		/* WatchpointHi */
#define C0_ECC		26		/* ECC */
#define C0_CACHEERR	27		/* CacheErr */
#define C0_TAGLO	28		/* TagLo */
#define C0_TAGHI	29		/* TagHi */
#define C0_ERREPC	30		/* ErrorEPC */
#endif /* R4000 */
#endif /* !LR33000 */

/* Floating-Point Control registers */
#define FPA_CSR		31		/* Control/Status register */
#define FPA_IRR		0		/* Implementation/Revision register */
#endif /* LANGUAGE_C */

/* Floating-Point Control register bits */
#define CSR_C		0x00800000
#define CSR_EXC		0x0003f000
#define CSR_EE		0x00020000
#define CSR_EV		0x00010000
#define CSR_EZ		0x00008000
#define CSR_EO		0x00004000
#define CSR_EU		0x00002000
#define CSR_EI		0x00001000
#define CSR_TV		0x00000800
#define CSR_TZ		0x00000400
#define CSR_TO		0x00000200
#define CSR_TU		0x00000100
#define CSR_TI		0x00000080
#define CSR_SV		0x00000040
#define CSR_SZ		0x00000020
#define CSR_SO		0x00000010
#define CSR_SU		0x00000008
#define CSR_SI		0x00000004
#define CSR_RM		0x00000003

/* Status Register */
#define SR_CUMASK	0xf0000000	/* Coprocessor usable bits */
#define	SR_CU3		0x80000000	/* Coprocessor 3 usable */
#define SR_CU2		0x40000000	/* coprocessor 2 usable */
#define SR_CU1		0x20000000	/* Coprocessor 1 usable */
#define SR_CU0		0x10000000	/* Coprocessor 0 usable */

#define SR_RE		0x02000000	/* Reverse Endian in user mode */
#define SR_BEV		0x00400000	/* Bootstrap Exception Vector */
#define SR_TS		0x00200000	/* TLB shutdown */

#ifndef R4000
/* R3000-specific bits */
#define SR_PE		0x00100000	/* Parity Error */
#define SR_CM		0x00080000	/* Cache Miss */
#define SR_PZ		0x00040000	/* Parity Zero */
#define SR_SWC		0x00020000	/* Swap Caches */
#define SR_ISC		0x00010000	/* Isolate Cache */

#define SR_KUO		0x00000020	/* Kernel/User mode, old */
#define SR_IEO		0x00000010	/* Interrupt Enable, old */
#define SR_KUP		0x00000008	/* Kernel/User mode, previous */
#define SR_IEP		0x00000004	/* Interrupt Enable, previous */
#define SR_KUC		0x00000002	/* Kernel/User mode, current */
#define SR_IEC		0x00000001	/* Interrupt Enable, current */
#else
/* R4000-specific bits */
#define SR_RP		0x08000000	/* Reduce Power */