starto.s.bak1

国产CPU－龙芯（loongson)BIOS源代码

#include <target/mips/reg.h>
#include <target/mips/mips.h>
#include <target/it8172.h>


############################################
#   lx-I.s - startup code for LX CPU       #
############################################


#define sr                      sw
#define lr                      lw
#define MTC0            mtc0
#define MFC0            mfc0
#define REGSZ           4
#define CACHELINE       16

#ifndef LOCAL_MEM
#define LOCAL_MEM       0
#endif

#if 1
#define __FULL_DBG              (0)
#endif

#define STKSIZE 0x3000

##############################################
#    some public entry, dont develop another #
#    useless one                             #
##############################################

#define MFC_NOP         nop; nop

###################
# RTC R & W       #
##################
#define RTCWrite(a,v) \
        li      t0, IT8172_PCI_IO_BASE + IT_RTC_BASE+IT_RTC_RIR0+KSEG1;\
        li      t1, (a); \
        sb      t1, (t0); \
        nop;    \
        li      t0, IT8172_PCI_IO_BASE + IT_RTC_BASE+IT_RTC_RTR0+KSEG1; \
        li      t1, (v); \
        sb      t1, (t0); \
        nop;

#define RTCRead(a) \
        li      t0, IT8172_PCI_IO_BASE + IT_RTC_BASE+IT_RTC_RIR0+KSEG1; \
        li      v0, a; \
        sb      v0,(t0); \
        nop;    \
        li      t0, IT8172_PCI_IO_BASE + IT_RTC_BASE+IT_RTC_RTR0+KSEG1; \
        lbu     v0,(t0); \
        nop;

#################
# gpio          #
#################
#define GPIO_LOOP       10000

#define MK_LAT(v)\
        li              t0, (v);        \
9:      subu    t0, 1;          \
        bne             t0, 0, 9b;      \
        nop;

#if 1
#define FLASH_GPIO(a)   \
        li      a0, (a)         ;\
        bal     __flash_gpio    ;\
        nop

#else
#define FLASH_GPIO(a)   \
        li      t1, 0xb4013802;\
        li      t0, 0x550       ;\
        sh      t0, (t1)        ;\
        subu    t1, t1, 2;\
        li      t0, (a)         ;\
        sll     t0, 2           ;\
        sb      t0, (t1);       \
        MK_LAT(GPIO_LOOP);
#endif

#   LEAF(flash_gpio)            #
#   is at the end of this file  #
#################################

################
# LED          #
###############
#define FLASH_LED(a)    \
        li      a0, (a)         ;\
        bal     __led_display   ;\
        nop

#       LED Display for ITE 8172 Chipset #
#       at the end of this file          #
##########################################

#################
# UART          #
#################
#define UART_OUTCH(a)   \
        bal     tgt_putchar      ;\
        li      a0, (a)

#################
# miscellaneous #
#################

#define HALT    \
8:      b       8b;     \
        nop;

#define WAIT(a) \
        li      t7, (a);\
9:      bnez t7, 9b;\
        subu t7, 1;

######################################
#  ROM Exception Entry               #
######################################

        .text
        .ent    reset_exception

reset_exception:

        .set noreorder
        .set noat

        b               start           # Reset Exception Entry
        move    k0, zero

        .set reorder
        .fill 0x380

        b               excHandler      # General Exception Entry, in ROM
                                        # it located at physaddr 0x1bfc0380
        .end    reset_exception


######################################
#               ROM BIOS Entry       #
######################################


        .comm   stack, STKSIZE          # Stack area
        .extern __led_display

        .set    at
        .globl  start
        .ent    start

start:                                  # This is the entry point of the BIOS ROM Image.
        .globl  __start
#        .aent   __start

__start:
        move    k0, zero

##########################################
#       Force Code to Run in K1 Seg.     #
#       Now the cache of CPU is invalid  #
##########################################
        .set    noreorder
        .set    nomacro

        bal             1f
        lui             t0, K1BASE>>16          # in fact, here a nop instruction inserted
1:      or              ra, t0                
        addiu           ra, 16                  # 16 = 4 * sizeof(LX-1 inst size).
        j               ra                      # now ra = . + 1
        nop

        .set    macro
        .set    reorder

######################################
#   Set Status&Cause&Watch Registers #
######################################
        .set noreorder
        mfc0    t0, C0_PRID                     # Get PRID, LX-1: 0x66
        mfc0    v0, C0_SR               # Get Status Reg
        MTC0    zero, C0_WATCHLO        # Clear Watch Regs
        MTC0    zero, C0_WATCHHI

        .set reorder
        and             v0, SR_SR       # Keep SoftReset bit, After a HardReset it will be 0.
        or              v0, SR_BEV      # Set BootExceptionVector bit to force it to use K1 Seg ROM space exception entry point.

        .set noreorder
        mtc0    v0, C0_SR                       # Set Status Reg.
        mtc0    zero, C0_CAUSE          # Clean CAUSE Reg.


######################################
#       Set up a K1seg stack         #
######################################
        .set reorder
1:      la      sp, stack + STKSIZE - 24
        or      sp, K1BASE

######################################
#   Calculate Re-location code       #
######################################

        bal             1f
1:      la              t1, 1b                  # Little trick to calculate relocation offset.
        subu            s8, ra, t1


######################################
#       Board Chipset Initialization #
######################################
#       bal             initChipset
#       nop
        mfc0    t1, C0_CONFIG                   # Get Config Reg
#####################################
#     Init Config Register          #
#####################################
        and             t1, ~0x3f               # Set Config Reg bits 5..0 only
        or              t1, CFG_IB \
                          | CFG_DB \
                          | CFG_C_WBACK         # Set Cache Mode related bits in Config Reg
        and             t1, ~CFG_BE             # Clean Big Endian bit in Config Reg

        /* set DDDD rate for CPUs that aren't hardware configured */
        and             t1, ~CFG_EPMASK         # Set EP 4 bits to 0 in Config Reg
        or              t1, CFG_EPD             # Set EP DataPattern 0
        and             t1, ~CFG_AD                             # ???
        mtc0    t1, C0_CONFIG           # Re-Set Config Reg bits

        mfc0    t1, C0_STATUS           # Get STATUS Reg
        mtc0    zero, C0_CAUSE          # Clean CAUSE Reg
        and             t1, SR_SR       #
        or              t1, SR_BEV      # Should be omited because it has been done before
        mtc0    t1, C0_STATUS           # Set STATUS Reg
        nop

        FLASH_GPIO(0x00)

#       RTCWrite(0x0a, 0x20)
#       RTCWrite(0x0b, 0x04)    # must enable the RTC in order to get refresh

#       li      t9, 0x03        /* 256Mb x 2 on cs0*/ /* 64M*/
        li      t9, 0x1B        # NC-it8172G on-board DIMM
#       li      t9, 0x12        /* 128Mb x 2 on cs0 cs1 */ /*32M*/

        sw      t9, ( IT_MC_SDTYPE + IT8172_BASE + KSEG1 )

#       FLASH_LED(0x01)
        FLASH_GPIO(0x01)

#################################
#   Read Memory Capacity and    #
# Update IT8172 related Register#
#################################
#if 0
        li      t9, 0x0301
        sh      t9, (KSEG1 + IT8172_BASE + IT_PCDCR)
        nop
        li      t9, 0x016B
        sh      t9, (KSEG1 + IT8172_BASE + IT_MC_SDRTR)
        nop
#       li      msize, 0x04000000       # 64MB
#else
        li      t9, 0x0300              # 4mA
#       li      t9, 0x0302              # 12mA
#       li      t9, 0x0301              #  8mA
#       li      t9, 0x0303              # 16mA
        sh      t9, (KSEG1 + IT8172_BASE + IT_PCDCR)
        nop

#       li      t9, 0x802B              # cas=2, burst length=8
        li      t9, 0x803B              # cas=3, burst length=8
        sh      t9, (KSEG1 + IT8172_BASE + IT_MC_SDRMR)
        nop


#       li      t9, 0x016B
#       li      t9, 0xffff
        li      t9, 0x01ff
        sh      t9, (KSEG1 + IT8172_BASE + IT_MC_SDRTR)
        nop

#       li      t9, 0x04
#       sw      t9, (KSEG1 + IT8172_BASE + 0x8)
#       nop

        li      t9, 0x1                 # open board
#       li      t9, 0x0                 # NC
        sh      t9, (KSEG1 + IT8172_BASE + IT_CMFPCR)    # change IT_CMFPCR
        nop

#       FLASH_LED(0x02)
        FLASH_GPIO(0x02)                # GPD 2..4 => 0001
#endif
#################################
#   Init COM Port in 8172G      #
#################################

        li              a0, KSEG1
        addu    a0, IT8172_PCI_IO_BASE
        addu    a0, IT_PM_DSR
        lh              a1, (a0)
        and             a1, ~0x0100
        sh              a1, (a0)        # Pull COM Port from standby mode

        li              a0, KSEG1
        addu    a0, IT8172_PCI_IO_BASE
        addu    a0, IT_UART_BASE        # Now a0 = NS16550 base register

        li              a1, 0x80        # set DLAB = 1
        addu    a2, a0, 3
        sb              a1, (a2)        # LCR (Line Control Register)

        li              a1, 0x01        # Baudrate = 115200
        addu    a2, a0, 0
        sb              a1, (a2)        # DLL (Divide Latch, LSB)

        li              a1, 0x03        # Enable FIFO&RCVR FIFO
        addu    a2, a0, 3
        sb              a1, (a2)        # LCR (Line Control Register)

        li              a1, 0x47        # RCVR Trigger & FIFO Enable
        addu    a2, a0, 2               # reset Tx/Rx Fifo
        sb              a1, (a2)        # FCR (Fifo Control Register)

        li              a1, 0x00        # Baudrate should be 0
        addu    a2, a0, 1
        sb              a1, (a2)        # DLM (Divisor Latch, MSB)

#       bal doMemTestX  # test SDRAM module

        nop
#       FLASH_LED(0x03)
        FLASH_GPIO(0x03)                # GPD 2..4 => 0001

######################################
#       ROM => RAM, Text RAM Section #
######################################
	la	a0, start
	li	a1, 0xbfc00000
	la	a2, _edata
	subu	t1, a2, a0
	srl t1, t1, 2

	/* copy text section */
	li	t0, 0
1:	lw	v0, 0(a1)
	nop
	sw	v0, 0(a0)
	addu	a0, 4
	bne a2, a0, 1b
	addu	a1, 4

        FLASH_GPIO(0x4)
######################################
#         Clean BSS sections         #
######################################
        .set    reorder
zbss:
        # clear bss
        la              v0, _fbss               # BSS section pre-compiled start in RAM
        la              v1, end                 # BSS section pre-compiled end in RAM
        or              v0, K1BASE
        or              v1, K1BASE

1:      .set    noreorder
        sw              $0, 0(v0)
        sw              $0, 4(v0)
        sw              $0, 8(v0)
        addu    v0, 16
        bltu    v0, v1, 1b
        sw              $0, -4(v0)              # use delay slot to fill 12(v0)

######################################
# Copy Exception Vectors to RAM      #
######################################
        .set    reorder
        la      a0, excHandler
        la      a1, eExcHandler
        li      a2, 0x0000180
        bal     copyExcVec
        nop

######################################
#         Init&Flush the Cache of CPU    #
######################################
#if 0
        jal             mips_init_cache
        jal             r4k_flush_cache
        nop
#else
        mfc0    t0, C0_CONFIG
        and     t0, 0xfffffff8
        or      t0, 0x2                 # disable,!default value is not it!
        mtc0    t0, C0_CONFIG                   # Set CPU to disable cache.
        nop

#endif

#       FLASH_LED(0x06)
        FLASH_GPIO(0x6)

######################################
# Re-set stack pointer for C code    #
######################################
        la      sp, stack + STKSIZE - 24        # Re-Set stack pointer

        la              t0, 1f                  # Switch from K1 Seg to K0 Seg.
        j               t0
1:      nop