startz.s.bad2

国产CPU－龙芯（loongson)BIOS源代码

/*	$Id: startz.S,v 1.2 2003/11/11 02:19:43 wlin Exp $ */

/*
 * Copyright (c) 2001 Opsycon AB  (www.opsycon.se)
 * 
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *	This product includes software developed by Opsycon AB, Sweden.
 * 4. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 */

#ifndef _KERNEL
#define _KERNEL
#endif

#include <target/it8172.h>
#include <asm.h>
#include <regnum.h>
#include <cpu.h>
#include <pte.h>




#define IndexInvalidate_I       0x00
#define IndexWriteBack_D        0x01


	.set	noreorder
	.globl	_start
	.globl	start
_start:
start:
#	bal 	Init_ITE_CPU
#	nop
	bal	locate
	nop
locate:
	subu	s8, ra, 0x8	/* Where we were loaded */
	la	sp, (.stack + 8192)

	la	a0, start	/* Where we were linked to run */
	move	a1, s8
	la	a2, _edata
	subu	t1, a2, a0
	srl	t1, t1, 2

	/* copy text section */
	li	t0, 0
1:	lw	v0, 0(a1)
	nop
	sw	v0, 0(a0)
	xor	t0, t0, v0
	addu	a0, 4
	bne	a2, a0, 1b
	addu	a1, 4


	
	/* Clear BSS */
	la	a0, _edata
	la	a1, _end
2:	sw	zero, 0(a0)
	bne	a1, a0, 2b
	addu	a0, 4

	move	a0, s8		     /* load address */
	move	a1, t1               /* length in words */

	la	ra, 1f
	la	k0, decompress_pmon
	jr	k0
	nop
1:

	li	k0, PMON_ENTRY
	jr	k0
	nop
3:
	b 3b
	.comm .stack,4096*2,4

LEAF(Init_ITE_CPU)
/* Initialize CPU */

        .set    macro
	.set noreorder
	mfc0    t0, COP_0_PRID
	mfc0    v0, COP_0_STATUS_REG 
	mtc0    zero, COP_0_WATCH_LO
	mtc0    zero, COP_0_WATCH_HI

	.set reorder
	and             v0, SR_SOFT_RESET
	or              v0, SR_BOOT_EXC_VEC

	.set noreorder
	mtc0    v0, COP_0_STATUS_REG
	mtc0    zero, COP_0_CAUSE_REG

#define CFG_IB		0x00000020
#define CFG_DB		0x00000010
#define	CFG_C_WBACK	3
#define CFG_BE		0x00008000
#define	FG_BE 		0x00008000
#define	CFG_EPMASK	0x0f000000
#define	CFG_EPD		0x00000000
#define	CFG_AD		0x00800000
/*
 * Initialize Configuration for board
 */
       	mfc0	   t1, COP_0_CONFIG                  # Get Config Reg
	nop

	and             t1, ~0x3f               # Set Config Reg bits 5..0 only
        or              t1, CFG_IB \
                          | CFG_DB \
                          | CFG_C_WBACK         # Set Cache Mode related bits in Config Reg
        and             t1, ~CFG_BE             # Clean Big Endian bit in Config Reg

        /* set DDDD rate for CPUs that aren't hardware configured */
        and             t1, ~CFG_EPMASK         # Set EP 4 bits to 0 in Config Reg
        or              t1, CFG_EPD             # Set EP DataPattern 0
        and             t1, ~CFG_AD                             # ???
        mtc0    t1, COP_0_CONFIG           # Re-Set Config Reg bits
	nop

        mfc0    t1, COP_0_STATUS_REG           
	nop
        mtc0    zero, COP_0_CAUSE_REG          
	nop
        and             t1, SR_SOFT_RESET       #
        or              t1, SR_BOOT_EXC_VEC      # Should be omited because it has been done before
        mtc0    t1, COP_0_STATUS_REG           # Set STATUS Reg
        nop



/*
 * Read Memory Capacity and Update IT8172 related Register
 */
	li	t9, 0x1b
	sw      t9, ( IT_MC_SDTYPE + IT8172_BASE + KSEG1 )
	nop

        li      t9, 0x0300              # 4mA
        sh      t9, (UNCACHED_MEMORY_ADDR + IT8172_BASE + IT_PCDCR)
        nop

        li      t9, 0x803B              # cas=3, burst length=8
        sh      t9, (UNCACHED_MEMORY_ADDR + IT8172_BASE + IT_MC_SDRMR)
        nop


        li      t9, 0x01ff
        sh      t9, (UNCACHED_MEMORY_ADDR + IT8172_BASE + IT_MC_SDRTR)
        nop


        li      t9, 0x1                 # open board
        sh      t9, (UNCACHED_MEMORY_ADDR + IT8172_BASE + IT_CMFPCR)    # change IT_CMFPCR
        nop
	move	ra, t4
	j 	ra
END(Init_ITE_CPU)