starto.s.a1

国产CPU－龙芯（loongson)BIOS源代码

/*	$Id: starto.S,v 1.7 2004/05/27 04:14:49 wlin Exp $ */

/*
 * Copyright (c) 2001 Opsycon AB  (www.opsycon.se)
 * 
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *	This product includes software developed by Opsycon AB, Sweden.
 * 4. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 */

#ifndef _KERNEL
#define _KERNEL
#endif

#include <asm.h>
#include <regnum.h>
#include <cpu.h>
#include <pte.h>

#include "target/it8172.h"

#include "pmon/dev/ns16550.h"

#ifdef GODSONEV2A
#	define SKIPDIMM
#	define SDRAM_MODE_FIX
#else
#	undef SKIPDIMM
#	undef SDRAM_MODE_FIX
#endif


#define DEBUG_LOCORE
#ifdef DEBUG_LOCORE
#define	TTYDBG(x) \
	.rdata;98: .asciz x; .text; la a0, 98b; bal stringserial; nop
#else
#define TTYDBG(x)
#endif

#define	PRINTSTR(x) \
	.rdata;98: .asciz x; .text; la a0, 98b; bal stringserial; nop



/*
 *   Register usage:
 *
 *	s0	link versus load offset, used to relocate absolute adresses.
 *	s1	free
 *	s2	base address to ITE chip.
 *	s3	L1 I cache size.
 *	s4	L1 I cache line size.
 *	s5	L1 D cache size.
 *	s6	L1 D cache line size.
 *	s7	L2 Cache size.
 *	s8	L3 Cache size.
 */


	.set	noreorder

	.globl	_start
	.globl	start
	.globl	__main
_start:
start:
	.globl	stack
stack = start - 0x4000		/* Place PMON stack below PMON start in RAM */

/* NOTE!! Not more that 16 instructions here!!! Right now it's FULL! */
	mtc0	zero, COP_0_STATUS_REG


	lui     a0,0x3000
	li      a1,SR_BOOT_EXC_VEC
	or      a0,a0,a1
	mtc0    a0, COP_0_STATUS_REG

	mtc0	zero, COP_0_CAUSE_REG
	la	sp, stack
	la	gp, _gp

	bal	uncached		/* Switch to uncached address space */
	nop

	bal	locate			/* Get current execute address */
	nop

uncached:
	or	ra, UNCACHED_MEMORY_ADDR
	j	ra
	nop

/*
 *  Reboot vector usable from outside pmon.
 */
	.align	8
ext_map_and_reboot:
	bal	CPU_TLBClear
	nop

	li	a0, 0xc0000000
	li	a1, 0x40000000
	bal	CPU_TLBInit
	nop
	la	v0, tgt_reboot
	la	v1, start
	subu	v0, v1
	lui	v1, 0xffc0
	addu	v0, v1
	jr	v0
	nop

/*
 *  Exception vectors here for rom, before we are up and running. Catch
 *  whatever comes up before we have a fully fledged exception handler.
 */
	.align	9			/* bfc00200 */
	la	a0, v200_msg
	bal	stringserial
	nop
	b	exc_common

	.align	7			/* bfc00280 */
	la	a0, v280_msg
	bal	stringserial
	nop
	b	exc_common

/* Cache error */
	.align	8			/* bfc00300 */
	PRINTSTR("\r\nPANIC! Unexpected Cache Error exception! ")
	mfc0	a0, COP_0_CACHE_ERR
	bal	hexserial
	nop
	b	exc_common

/* General exception */
	.align	7			/* bfc00380 */

/* make keg0 uncached to make sure prints works! */
#if 0
        mfc0    a0,COP_0_CONFIG
        and    a0,a0,0xfffffff8
        or     a0,a0,0x2
	mtc0   a0,COP_0_CONFIG
#endif
#if 1
	lui a1, 0xa040
        nop
	mfc0 a0, COP_0_EXC_PC
        nop
	sw a0, (a1)
        nop
	mfc0 a0, COP_0_CAUSE_REG
        nop
	sw a0, (a1)
        nop
	dmfc0 a0, $8
        nop
	dsrl a0,a0,32
        nop
	sw a0, (a1)
        nop
	mfc0 a0, $8
        nop
	sw a0, (a1)
        nop

	mfc0 a0, COP_0_EXC_PC
	nop
	lw a0, (a0)
	nop
	sw a0, (a1)
	nop

#endif

	la	a0, v380_msg
	bal	stringserial
	nop
	b	exc_common

	.align	8			/* bfc00400 */
	la	a0, v400_msg
	bal	stringserial
	nop

exc_common:
	PRINTSTR("\r\nERRORPC=")
	mfc0	a0, COP_0_ERROR_PC
	bal	hexserial
	nop
	PRINTSTR("\r\nEPC=")
	mfc0	a0, COP_0_EXC_PC
	bal	hexserial
	nop
	PRINTSTR("\r\n(EPC)=")
	mfc0	a0, COP_0_EXC_PC
	lw	a0, (a0)
	bal	hexserial
	nop

	PRINTSTR("\r\nSTATUS=")
	mfc0	a0, COP_0_STATUS_REG
	bal	hexserial
	nop
	PRINTSTR("\r\nCAUSE=")
	mfc0	a0, COP_0_CAUSE_REG
	bal	hexserial
	nop
	PRINTSTR("\r\nBADVADDR=")
	dmfc0	a0, $8
        dsrl  a0,a0,32
	bal	hexserial
        nop
	dmfc0	a0, $8
	bal	hexserial
	nop

	PRINTSTR("\r\nDERR0=")
	cfc0	a0, COP_0_DERR_0
	bal	hexserial
	nop
	PRINTSTR("\r\nDERR1=")
	cfc0	a0, COP_0_DERR_1
	bal	hexserial
	nop
	
	1:	 b  1b
        nop
	 
//	b	ext_map_and_reboot
	nop

/*
 * gpio function define         
 */
#define GPIO_LOOP       10000

#define MK_LAT(v)\
        li              t0, (v);        \
9:      subu    t0, 1;          \
        bne             t0, 0, 9b;      \
        nop;

#if 1
#define FLASH_GPIO(a)   \
        li      a0, (a)         ;\
        bal     __flash_gpio    ;\
        nop

#else
#define FLASH_GPIO(a)   \
        li      t1, 0xb4013802;\
        li      t0, 0x550       ;\
        sh      t0, (t1)        ;\
        subu    t1, t1, 2;\
        li      t0, (a)         ;\
        sll     t0, 2           ;\
        sb      t0, (t1);       \
        MK_LAT(GPIO_LOOP);
#endif

/* 
 * LED      
 */    
#define FLASH_LED(a)    \
        li      a0, (a)         ;\
        bal     __led_display   ;\
        nop




/*
 *  We get here from executing a bal to get the PC value of the current execute
 *  location into ra. Check to see if we run from ROM or if this is ramloaded.
 */
	.align 8    /*bfc00500*/
	.word read
	.word write
	.word open
	.word close
	.word nullfunction
	.word printf
	.word vsprintf
	.word nullfunction
	.word nullfunction
	.word getenv
	.word nullfunction
	.word nullfunction
	.word nullfunction
	.word nullfunction

	
locate:
	bal init_regs
	nop
	FLASH_GPIO(1)


	la	s0, start		/* RA set from BAL above! */
	subu	s0, ra, s0		/* s0 is now load vs. link offset */
	and	s0, 0xffff0000		/* Mask off lower bits */

/*
 *  Clean out and initialize the TLB
 */
	bal	CPU_TLBClear
	nop

	li	a0, 0xc0000000
	li	a1, 0x40000000
	bal	CPU_TLBInit
	nop



#define CFG_IB		0x00000020
#define CFG_DB		0x00000010
#define	CFG_C_WBACK	3
#define CFG_BE		0x00008000
#define	FG_BE 		0x00008000
#define	CFG_EPMASK	0x0f000000
#define	CFG_EPD		0x00000000
#define	CFG_AD		0x00800000
######################################
#       Board Chipset Initialization #
######################################
#       bal             initChipset
#       nop
       	mfc0	   t1, COP_0_CONFIG                  # Get Config Reg

#####################################
#     Init Config Register          #
#####################################
	and             t1, ~0x3f               # Set Config Reg bits 5..0 only
        or              t1, CFG_IB \
                          | CFG_DB \
                          | CFG_C_WBACK         # Set Cache Mode related bits in Config Reg
        and             t1, ~CFG_BE             # Clean Big Endian bit in Config Reg

        /* set DDDD rate for CPUs that aren't hardware configured */
        and             t1, ~CFG_EPMASK         # Set EP 4 bits to 0 in Config Reg
        or              t1, CFG_EPD             # Set EP DataPattern 0
        and             t1, ~CFG_AD                             # ???
        mtc0    t1, COP_0_CONFIG           # Re-Set Config Reg bits

        mfc0    t1, COP_0_STATUS_REG           
        mtc0    zero, COP_0_CAUSE_REG          
        and             t1, SR_SOFT_RESET       #
        or              t1, SR_BOOT_EXC_VEC      # Should be omited because it has been done before
        mtc0    t1, COP_0_CONFIG           # Set STATUS Reg
        nop

	FLASH_GPIO(2)
	li	t9, 0x1b
	sw      t9, ( IT_MC_SDTYPE + IT8172_BASE + KSEG1 )
	nop


/*
 * Read Memory Capacity and Update IT8172 related Register
 */
        li      t9, 0x0300              # 4mA
        sh      t9, (UNCACHED_MEMORY_ADDR + IT8172_BASE + IT_PCDCR)
        nop

        li      t9, 0x803B              # cas=3, burst length=8
        sh      t9, (UNCACHED_MEMORY_ADDR + IT8172_BASE + IT_MC_SDRMR)
        nop


        li      t9, 0x01ff
        sh      t9, (UNCACHED_MEMORY_ADDR + IT8172_BASE + IT_MC_SDRTR)
        nop


        li      t9, 0x1                 # open board
        sh      t9, (UNCACHED_MEMORY_ADDR + IT8172_BASE + IT_CMFPCR)    # change IT_CMFPCR
        nop

        FLASH_GPIO(0x03)                # GPD 2..4 => 0001

/*
 *  Init serial I/O for diagnostic output.
 */
        bal     initserial
        nop

        PRINTSTR("\r\nPMON2000 MIPS Initializing. Standby...\r\n")

        PRINTSTR("ERRORPC=")
        mfc0    a0, COP_0_ERROR_PC
        bal     hexserial
        nop

        FLASH_GPIO(0x04)                # GPD 2..4 => 0001
        PRINTSTR(" CONFIG=")
        mfc0    a0, COP_0_CONFIG
        bal     hexserial
        nop
        PRINTSTR("\r\n")

        la      s0, start               /* RA set from BAL above! */
        subu    s0, ra, s0              /* s0 is now load vs. link offset */
        and     s0, 0xffff0000          /* Mask off lower bits */


        TTYDBG("Setting up SDRAM controller\r\n");


/*
 *  Reset and initialize caches to a known state.
 */
#define IndexStoreTagI	0x08
#define IndexStoreTagD	0x09
#define IndexStoreTagS	0x0b
#define IndexStoreTagT	0x0a
#define FillI		0x14

/*
 *  RM7000 config register bits.
 */
#define CPU_CONFIG	0x00
#define CF_7_SE         (1 << 3)        /* Secondary cache enable */
#define CF_7_SC         (1 << 31)       /* Secondary cache not present */
#define CF_7_TE         (1 << 12)       /* Tertiary cache enable */
#define CF_7_SCD	(1 << 13)	/* extend DCE interface signal by one cycle in the CPU */
#define CF_7_TC         (1 << 17)       /* Tertiary cache not present */
#define CF_7_TS         (3 << 20)       /* Tertiary cache size */
#define CF_7_TS_AL      20              /* Shift to align */
#define	GT_CPU_R7KL3	(1 << 14)	/* R7KL3 present*/
#define NOP8 nop;nop;nop;nop;nop;nop;nop;nop
do_caches:
	TTYDBG("Sizing caches...\r\n");

	mfc0	t3, COP_0_CONFIG	/* t3 = original config */
	and	t3, 0xffffeff0		/* Make sure coherency is OK */

	and	t3, ~(CF_7_TE|CF_7_SE|CF_7_TC|CF_7_SC)  /* disable L2/L3 cache */
	mtc0    t3, COP_0_CONFIG

	li	t2, 4096

	srl	t1, t3, 9
	and	t1, 7
	sllv	s3, t2, t1		/* s3 = I cache size */

#ifdef CONFIG_CACHE_64K_4WAY
	sll 	s3,2
#endif

	and	t1, t3, 0x20
	srl	t1, t1, 1
	addu	s4, t1, 16		/* s4 = I cache line size */

	srl	t1, t3, 6
	and	t1, 7
	sllv	s5, t2, t1		/* s5 = D cache size */

#ifdef CONFIG_CACHE_64K_4WAY
	sll 	s5,2
#endif

	and	t1, t3, 0x10
	addu	s6, t1, 16		/* s6 = D cache line size */
	TTYDBG("Init caches...\r\n")

	li	s7, 0                   /* no L2 cache */
	li	s8, 0                   /* no L3 cache */

	mfc0    a0, COP_0_PRID
	and 	a0, a0, 0xff00
	li      a1, 0x6300
	bne     a0,a1,1f
	nop
	TTYDBG("godson2 caches found\r\n")
        bal     godson2_cache_init
        nop

#ifdef CONFIG_GODSON_SECONDARY_CACHE

	li	s7, 0x200000

	TTYDBG("Init Godson L3 cache...\r\n")
                                                                                                                                                            
        or      t3, (CF_7_TE|CF_7_SCD)          /* Enable secondary cache */
        mtc0    t3, COP_0_CONFIG
        NOP8
	lw	t0, CPU_CONF(s2)
	or	t0, GT_CPU_R7KL3		/* Enable R7KL3 */
	sw	t0, CPU_CONF(s2)		
	
        li      a0, 0
        add     a1, a0, s7                      /* End = size of L2 cache */
1:	
	bal	invalidate_external_cache_page
	nop
	addu 	a0, a0, 4096
	bne	a0, a1, 1b
	nop                                                                                                                                   
#endif
	
	b	cache_done
	nop
1:

#if 0

	and	t1, t3, CF_7_TC
	bnez	t1, Conf7KL2		/* Any L3 disabled if set */
	li	s8, 0

	li	s8, 1024 * 1024 * 2
#if 0
	li	t0, CF_7_TS		/* Use when cache size is in cfg reg */
	and	t1, t3, t0
	beq	t1, t0, Conf7KL2
	srl	t1, CF_7_TS_AL

	li	s8, 5024288		/* 512k */
	sll	s8, t1
#endif

Conf7KL2:
	and	t1, t3, CF_7_SC
	bnez	t1, Conf7KEnd
	li	s7, 0

	li	s7, 262144		/* Size of L2 cache */

#endif
	li      s7,0
	li      s8,0

Conf7KEnd:

	TTYDBG("Disable cache exceptions...\r\n");

	mfc0	t0, COP_0_STATUS_REG
	and	t1, t0, SR_BOOT_EXC_VEC
	or	t1, SR_DIAG_DE
	mtc0	t1, COP_0_STATUS_REG

	mtc0	zero, COP_0_TAG_LO
	mtc0	zero, COP_0_TAG_HI
	mtc0	zero, COP_0_ECC

	and	t2, t3, ~(CF_7_SE|CF_7_TE)
	mtc0	t2, COP_0_CONFIG		/* Disable L2 and L3 */
	NOP8

/*
 *  Do L1 instruction cache.
 */

	TTYDBG("Init L1 instruction cache...\r\n")

	la	a0, CACHED_MEMORY_ADDR
	addu	a1, a0, s3			/* End = size of I cache */

1:
	addu	a0, s4				/* Step by line size */
	cache	IndexStoreTagI, -4(a0)
	nop
	cache	FillI, -4(a0)
	nop
	bne	a0, a1, 1b
	cache	IndexStoreTagI, -4(a0)

/*
 *  Do L1 data cache.
 */

	TTYDBG("Init L1 data cache...\r\n")