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来自「国产CPU-龙芯(loongson)BIOS源代码」· 代码 · 共 845 行
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845 行
# 1 "/home/fxzhang/software/pmon/src/Targets/gfcr/gfcr/start.S"# 1 "machine/asm.h" 1 # 1 "machine/regdef.h" 1 # 51 "machine/asm.h" 2 # 83 "machine/asm.h" # 115 "machine/asm.h" # 1 "/home/fxzhang/software/pmon/src/Targets/gfcr/gfcr/start.S" 2# 1 "/home/fxzhang/software/pmon/src/Targets/gfcr/include/mipsregs.h" 1 # 2 "/home/fxzhang/software/pmon/src/Targets/gfcr/gfcr/start.S" 2# 1 "/home/fxzhang/software/pmon/src/Targets/gfcr/include/address.h" 1 # 3 "/home/fxzhang/software/pmon/src/Targets/gfcr/gfcr/start.S" 2 ##################UART #########################################################ROM Exception Entry ####################################### .text .ent reset_exceptionreset_exception: .set noreorder .set noat b start # Reset Exception Entry move $26 , $0 .set reorder .org 0x380 b excHandler # General Exception Entry, in ROM #it located at physaddr 0x1bfc0380 .end reset_exception #######################################ROM BIOS Entry ####################################### .comm stack, 0x3000 # Stack area .set at .globl start .ent startstart: # This is the entry point of the BIOS ROM Image. .globl __start .aent __start__start: move $26 , $0 ###########################################Force Code to Run in K1 Seg. ##Now the cache of CPU is invalid ########################################### .set noreorder .set nomacro bal 1f lui $8 , 0xa0000000 >>16 # in fact, here a nop instruction inserted1: or $31 , $8 # by compiler in case of the delay slot's effect. addiu $31 , 16 # 16 = 4 * sizeof(LX-1 inst size). j $31 # now $31 = . + 1 nop .set macro .set reorder #######################################Set up a K1seg stack ####################################### .set reorder1: la $29 , stack + 0x3000 - 24 or $29 , $29 , 0xa0000000 #######################################Calculate Re-location code ####################################### bal 1f1: la $9 , 1b # Little trick to calculate relocation offset. subu $30 , $31 , $9 # 126 "/home/fxzhang/software/pmon/src/Targets/gfcr/gfcr/start.S"#################################Initailize SDRAM Interface ################################# li $4 ,0xbf000000#config li $5 , 0x20000000 sw $5 ,4($4 )#timing li $5 ,0x01040242 sw $5 ,0($4 )#config li $5 , 0x209800c6 sw $5 ,4($4 )#bal doMemTestX # test SDRAM module#######################################ROM => RAM, Text RAM Section ####################################### la $8 , _ftextram add $8 , $30 # $8 = ROM addr of text segs' end la $9 , _ftextram # $9 destination $9 or $9 , 0xa0000000 la $10 , _etextram # $10 is the length of textram+rodat segs. or $10 , 0xa0000000 addu $10 , 4 - 1 and $10 , - 4 # end address aligned .set noreorder1: lw $11 , 0($8 ) # $11 : source context addu $8 , 4 # $8 : source address register addu $9 , 4 # $9 : destination address register bne $9 , $10 , 1b # $10 : end address register sw $11 , - 4 ($9 )#######################################ROM => RAM, Data Sections ####################################### .set reorder2: la $8 , _etextram addu $8 , $30 # RELOC or $8 , 0xa0000000 # $8 : data section start address in ROM addu $8 , 32 -1 and $8 , - 32 la $9 , _fdata or $9 , 0xa0000000 # $9 : data section start address in RAM la $10 , _edata or $10 , 0xa0000000 # $10 : data section end address in RAM addu $10 , 4 -1 and $10 , - 4 beq $9 , $10 , zbss .set noreorder1: lw $11 , 0($8 ) addu $8 , 4 addu $9 , 4 bne $9 , $10 , 1b sw $11 , - 4 ($9 )#######################################Clean BSS sections ####################################### .set reorderzbss: #clear bss la $2 , _fbss # BSS section pre-compiled start in RAM la $3 , end # BSS section pre-compiled end in RAM or $2 , 0xa0000000 or $3 , 0xa0000000 1: .set noreorder sw $0, 0($2 ) sw $0, 4($2 ) sw $0, 8($2 ) addu $2 , 16 bltu $2 , $3 , 1b sw $0, -4($2 ) # use delay slot to fill 12($2 )#######################################Copy Exception Vectors to RAM ####################################### .set reorder la $4 , excHandler la $5 , eExcHandler li $6 , 0x0000180 bal copyExcVec nop#######################################Disable Interrupt ####################################### mfc0 $8 , $12 and $8 , 0xfffffffe # By default it will be disabled. mtc0 $8 , $12 # Set CPU to disable interrupt. nop #######################################Init&Flush the Cache of CPU ####################################### mfc0 $8 , $16 and $8 , 0xfffffff8 or $8 , 0x2 # disable,!default value is not it! mtc0 $8 , $16 # Set CPU to disable cache. nop#######################################Re-set stack pointer for C code ####################################### la $29 , stack + 0x3000 - 24 # Re-Set stack pointer#######################################Jump to normal BIOS startup code # #######################################la $4 , start_bios la $4 , initmips jr $4 nop 1: bal 1b j start .end start###################################################copyExcVec Function Entry ####Params: ##a0 = Src ExcVec Start Addr ##a1 = Src ExcVec End Addr ##a2 = Dst ExcVec Addr ##Volatile: ##a0, $5 ################################################### .globl copyExcVec .ent copyExcVec copyExcVec: or $8 , $4 , 0xa0000000 # Force $4 & $5 to K1 Seg or $9 , $5 , 0xa0000000 or $6 , 0xa0000000 # Although $6 in K1, but it's in RAM1: lw $2 , ($8 ) sw $2 , ($6 ) addu $8 , 4 addu $6 , 4 bltu $8 , $9 , 1b j $31 .end copyExcVec#######################################General Exception Handler Entry ####################################### .globl excHandler .ent excHandlerexcHandler: .set noat .rdata;98: .asciz "EXCEPTION!CAUSE=" ; .text; la $4 , 98b; bal puts; nop ; mfc0 $4 , $13 la $9 , put32 jalr $9 nop .rdata;98: .asciz " EPC=" ; .text; la $4 , 98b; bal puts; nop ; mfc0 $4 , $14 la $9 , put32 jalr $9 nop .rdata;98: .asciz " BADVADDR=" ; .text; la $4 , 98b; bal puts; nop ; mfc0 $4 , $8 la $9 , put32 jalr $9 nop .rdata;98: .asciz " STATUS=" ; .text; la $4 , 98b; bal puts; nop ; mfc0 $4 , $12 la $9 , put32 jalr $9 nop .set mips3 eret .set mips0eExcHandler: # End of General Exception Handler .set at .end excHandler .align 3; .globl tgt_putchar ; .ent tgt_putchar , 0; tgt_putchar : ; .frame $29 , 0, $31 ; li $8 , (0x13) # timeout1: lbu $9 , ((0xa0000000 + 0x1f004090 + 0x5) ) # get LSR and $9 , 0x20 # tx ready? bnez $9 , 1f # can write2: li $9 , (0x12) # Wait a while3: subu $9 , 1 bnez $9 , 3b subu $8 , 1 # continue until timeout bnez $8 , 1b1: sb $4 , ((0xa0000000 + 0x1f004090 + 0x0) ) # write data j $31 nop.end tgt_putchar #######################################Print 32bit Integer in reg $4 #######################################.align 3; .globl put32 ; .ent put32 , 0; put32 : ; .frame $29 , 0, $31 ; .set noreorder move $25 , $31 move $14 , $4 li $15 , 322: subu $15 , 4 srl $4 , $15 and $4 , 0x0F blt $4 , 0x0A, 3f nop subu $4 , 0x0a addu $4 , 'A' j 4f nop3: addu $4 , '0'4: bal tgt_putchar nop move $4 , $14 bnez $15 , 2b nop move $31 , $25 j $31 nop .set reorder.end put32 .align 3; .globl puts ; .ent puts , 0; puts : ; .frame $29 , 0, $31 ; .set noreorder move $25 , $31 move $5 , $4 lbu $4 , 0($5 )1: beqz $4 , 2f nop bal tgt_putchar addiu $5 , 1 b 1b lbu $4 , 0($5 )2: j $25 nop .set reorder.end puts #######################################Test SDRAM Module #######################################.align 3; .globl doMemTestX ; .ent doMemTestX , 0; doMemTestX : ; .frame $29 , 0, $31 ; .set macro .set noreorder move $25 , $31 .rdata;98: .asciz "\r\nSDRAM Testing..." ; .text; la $4 , 98b; bal puts; nop ; li $5 , 0x0 li $6 , 0x0 li $7 , 0x0 li $16 , 0x1 li $17 , 0x2 li $18 , 0x3 li $19 , 0x4 nop li $10 , (0xA0000000) li $11 , (0xA8000000) 1: sw $16 , ($10 ) sh $17 , 4($10 ) sb $18 , 6($10 ) move $4 , $10 nop bal put32 nop .rdata;98: .asciz "\r\n" ; .text; la $4 , 98b; bal puts; nop lw $19 , ($10 ) bne $19 , $16 , 3f nop lhu $20 , 4($10 ) and $12 , $17 , 0xffff bne $20 , $12 , 3f nop lbu $21 , 6($10 ) and $12 , $18 , 0xff bne $21 , $12 , 3f nop 2: addiu $10 , (0x01000) addiu $16 , 0x1 addiu $17 , 0x1 addiu $18 , 0x1 bne $10 , $11 , 1b nop .rdata;98: .asciz "\r\nTest end.\r\n" ; .text; la $4 , 98b; bal puts; nop move $31 , $25 j $31 nop#########################some error occured ! #########################3: .rdata;98: .asciz "\r\nMISMATCH at locate:" ; .text; la $4 , 98b; bal puts; nop move $4 , $10 nop bal put32 nop .rdata;98: .asciz "\r\nExpect:" ; .text; la $4 , 98b; bal puts; nop move $4 , $16 bal put32 nop bal tgt_putchar ; li $4 , ( ' ' ) move $4 , $17 bal put32 nop bal tgt_putchar ; li $4 , ( ' ' ) move $4 , $18 bal put32 nop .rdata;98: .asciz " Got:" ; .text; la $4 , 98b; bal puts; nop move $4 , $19 bal put32 nop bal tgt_putchar ; li $4 , ( ' ' ) move $4 , $20 bal put32 nop bal tgt_putchar ; li $4 , ( ' ' ) move $4 , $21 bal put32 nop .rdata;98: .asciz "\r\n" ; .text; la $4 , 98b; bal puts; nop b 2b nop .set reorder.end doMemTestX
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