ethernet.h

国产CPU－龙芯（loongson)BIOS源代码

#include <types.h>

#define MAC_REG_BASE	0x1f002000
/*
 * MAC Controller
 */                                             
/* Data structure  for Tx BD */
#define BIT_MAC_TX_BD_READY    	 0x00008000	     // Tx BD Ready
#define BIT_MAC_TX_BD_IRQ      	 0x00004000	     // Tx BD IRQ Enable
#define BIT_MAC_TX_BD_WRAP     	 0x00002000	    // Tx BD Wrap (last BD)
#define BIT_MAC_TX_BD_PAD      	 0x00001000	     // Tx BD Pad Enable
#define BIT_MAC_TX_BD_CRC      	 0x00000800	     // Tx BD CRC Enable

#define BIT_MAC_TX_BD_UNDERRUN 	 0x00000100	     // Tx BD Underrun Status
#define BIT_MAC_TX_BD_RETRY    	 0x000000F0	     // Tx BD Retry Status
#define BIT_MAC_TX_BD_RETLIM   	 0x00000008	     // Tx BD Retransmission Limit Status
#define BIT_MAC_TX_BD_LATECOL  	 0x00000004	     // Tx BD Late Collision Status
#define BIT_MAC_TX_BD_DEFER    	 0x00000002	     // Tx BD Defer Status
#define BIT_MAC_TX_BD_CARRIER  	 0x00000001	     // Tx BD Carrier Sense Lost Status

#define DIS_TXBD_BUF		 0x400		     // Tx BD offset to MAC regster base

/* Rx BD */                                           
#define BIT_MAC_RX_BD_EMPTY    	 0x00008000	    // Rx BD Empty
#define BIT_MAC_RX_BD_IRQ      	 0x00004000	    // Rx BD IRQ Enable
#define BIT_MAC_RX_BD_WRAP     	 0x00002000	    // Rx BD Wrap (last BD)

#define BIT_MAC_RX_BD_MISS     	 0x00000080	     // Rx BD Miss Status
#define BIT_MAC_RX_BD_OVERRUN  	 0x00000040	     // Rx BD Overrun Status
#define BIT_MAC_RX_BD_INVSIMB  	 0x00000020	     // Rx BD Invalid Symbol Status
#define BIT_MAC_RX_BD_DRIBBLE  	 0x00000010	     // Rx BD Dribble Nibble Status
#define BIT_MAC_RX_BD_TOOLONG  	 0x00000008	     // Rx BD Too Long Status
#define BIT_MAC_RX_BD_SHORT    	 0x00000004	     // Rx BD Too Short Frame Status
#define BIT_MAC_RX_BD_CRCERR   	 0x00000002	     // Rx BD CRC Error Status
#define BIT_MAC_RX_BD_LATECOL  	 0x00000001	     // Rx BD Late Collision Status

// MAC Controller                                
#define REG_MAC_MODER           	 0x00000000	     // 0x00 
#define BIT_MAC_MODER_RXEN      	 0x00000001	 // Receive Enable
#define BIT_MAC_MODER_TXEN      	 0x00000002	 // Transmit Enable
#define BIT_MAC_MODER_NOPRE     	 0x00000004	 // No Preamble
#define BIT_MAC_MODER_BRO       	 0x00000008	 // Reject Broadcast
#define BIT_MAC_MODER_IAM       	 0x00000010	 // Use Individual Hash
#define BIT_MAC_MODER_PRO       	 0x00000020	 // Promiscuous (receive all)
#define BIT_MAC_MODER_IFG       	 0x00000040	 // Min. IFG not required
#define BIT_MAC_MODER_LOOPBCK   	 0x00000080	 // Loop Back
#define BIT_MAC_MODER_NOBCKOF   	 0x00000100	 // No Backoff
#define BIT_MAC_MODER_EXDFREN   	 0x00000200	 // Excess Defer
#define BIT_MAC_MODER_FULLD     	 0x00000400	 // Full Duplex
#define BIT_MAC_MODER_RST       	 0x00000800	 // Reset MAC
#define BIT_MAC_MODER_DLYCRCEN  	 0x00001000	 // Delayed CRC Enable
#define BIT_MAC_MODER_CRCEN     	 0x00002000	 // CRC Enable
#define BIT_MAC_MODER_HUGEN     	 0x00004000	 // Huge Enable
#define BIT_MAC_MODER_PAD       	 0x00008000	 // Pad Enable
#define BIT_MAC_MODER_RECSMALL  	 0x00010000	 // Receive Small
#define BIT_MAC_SOFT_RST        	 0x00800000	 // Soft reset for MAC

/* Interrupt relative */
#define REG_MAC_INT_SOURCE      	 0x00000004	     // 0x04
#define BIT_MAC_INT_TXB         	 0x00000001	 // Transmit Buffer IRQ          
#define BIT_MAC_INT_TXE         	 0x00000002	 // Transmit Error IRQ           
#define BIT_MAC_INT_RXB         	 0x00000004	 // Receive Buffer IRQ           
#define BIT_MAC_INT_RXE         	 0x00000008	 // Receive Error IRQ            
#define BIT_MAC_INT_BUSY        	 0x00000010	 // Busy IRQ                    
#define BIT_MAC_INT_TXC         	 0x00000020	 // Transmit Control Frame IRQ   
#define BIT_MAC_INT_RXC         	 0x00000040	 // Received Control Frame IRQ        

#define REG_MAC_INT_MASK        	 0x00000008	     // 0x08 
#define BIT_MAC_INT_MASK_TXB    	 0x00000001	 // Transmit Buffer IRQ Mask 
#define BIT_MAC_INT_MASK_TXE    	 0x00000002	 // Transmit Error IRQ Mask 
#define BIT_MAC_INT_MASK_RXF    	 0x00000004	 // Receive Frame IRQ Mask 
#define BIT_MAC_INT_MASK_RXE    	 0x00000008	 // Receive Error IRQ Mask 
#define BIT_MAC_INT_MASK_BUSY   	 0x00000010	 // Busy IRQ Mask 
#define BIT_MAC_INT_MASK_TXC    	 0x00000020	 // Transmit Control Frame IRQ Mask 
#define BIT_MAC_INT_MASK_RXC    	 0x00000040	 // Received Control Frame IRQ Mask 

/* MAC relative */
#define REG_MAC_IPGT            	 0x0000000C	     // 0x0C 
#define REG_MAC_IPGR1           	 0x00000010	     // 0x10
#define REG_MAC_IPGR2           	 0x00000014	     // 0x14
#define REG_MAC_PACKETLEN       	 0x00000018	     // 0x18
#define REG_MAC_COLLCONF        	 0x0000001C	     // 0x1C
#define REG_MAC_TX_BD_NUM       	 0x00000020	     // 0x20
#define REG_MAC_CTRLMODER       	 0x00000024	     // 0x24   
#define BIT_MAC_CTRLMODER_PASSALL	 0x00000001	// Pass Control Frames 
#define BIT_MAC_CTRLMODER_RXFLOW	 0x00000002	 // Receive Control Flow Enable 
#define BIT_MAC_CTRLMODER_TXFLOW	 0x00000004	 // Transmit Control Flow Enable 

#define REG_MAC_MIIMODER        	 0x00000028	     // 0x28 
#define BIT_MAC_MIIMODER_CLKDIV 	 0x000000FF	 // Clock Divider
#define BIT_MAC_MIIMODER_NOPRE  	 0x00000100	 // No Preamble
#define BIT_MAC_MIIMODER_RST    	 0x00000200	 // MIIM Reset 

#define REG_MAC_MIICOMMAND      	 0x0000002C	     // 0x2C
#define BIT_MAC_MIICMD_SCANSTAT 	 0x00000001	 // Scan Status 
#define BIT_MAC_MIICMD_RSTAT    	 0x00000002	 // Read Status 
#define BIT_MAC_MIICMD_WCTRLDATA	 0x00000004	 // Write Control Data 

#define REG_MAC_MIIADDRESS      	 0x00000030	     // 0x30    
#define BIT_MAC_MIIADDRESS_FIAD 	 0x0000001F	 // PHY Address 
#define BIT_MAC_MIIADDRESS_RGAD 	 0x00001F00	 // RGAD Address

#define REG_MAC_MIITX_DATA      	 0x00000034	     // 0x34
#define REG_MAC_MIIRX_DATA      	 0x00000038	     // 0x38
#define REG_MAC_MIISTATUS       	 0x0000003C	     // 0x3C
#define BIT_MAC_MIISTAT_LINKFAIL	0x00000001	  // Link Fail bit
#define BIT_MAC_MIISTAT_BUSY    	0x00000002	  // MII Busy bit 
#define BIT_MAC_MIISTAT_NVALID  	0x00000004	  // Data in MII Status Register is invalid bit 

#define REG_MAC_ADDR0           	 0x00000040	     // 0x40
#define REG_MAC_ADDR1           	 0x00000044	     // 0x44
#define REG_MAC_HASH0           	 0x00000048	     // 0x48
#define REG_MAC_HASH1           	 0x0000004C	     // 0x4C
#define REG_MAC_TX_CTRL         	 0x00000050	     // 0x50    
#define BIT_MAC_TX_CTRL_PAUSERQ 	 0x00010000	 // Send PAUSE request
#define REG_MAC_BD_BASE         	 0x00000400	     // 0x400

#define SD_MAC_TX_BASE        	 0x50000	   
#define SD_MAC_TX_SIZE        	 0x08000	   
#define SD_MAC_RX_BASE        	 0x58000
#define SD_MAC_RX_SIZE        	 0x08000

#define TOTAL_BD_NUM          	 128	       
#define MAC_ADDRESS_HI        	 0x0000AA02	
#define MAC_ADDRESS_LO        	 0x03040506	

#define MIN_FL                	 64	
#define MAX_FL                	 1518	 


/* Common define */
#define ETH_SET32(idx, value) KSEG1_STORE32(MAC_REG_BASE + idx, (u32)value)
#define ETH_GET32(idx) KSEG1_LOAD32(MAC_REG_BASE + idx)

#define DEST_ADDR(frame, addr1, addr2) \
    frame->des_addr[0] = (unsigned long)(addr2) & 0xff; \
    frame->des_addr[1] = ((unsigned long)(addr2) >> 0x08) & 0xff; \
    frame->des_addr[2] = ((unsigned long)(addr2) >> 0x10) & 0xff; \
    frame->des_addr[3] = (unsigned long)(addr1) & 0xff; \
    frame->des_addr[4] = ((unsigned long)(addr1) >> 0x08) & 0xff; \
    frame->des_addr[5] = ((unsigned long)(addr1) >> 0x10) & 0xff; 

#define SRC_ADDR(frame, addr1, addr2) \
    frame->src_addr[0] = (unsigned long)(addr2) & 0xff; \
    frame->src_addr[1] = ((unsigned long)(addr2) >> 0x08) & 0xff; \
    frame->src_addr[2] = ((unsigned long)(addr2) >> 0x10) & 0xff; \
    frame->src_addr[3] = (unsigned long)(addr1) & 0xff; \
    frame->src_addr[4] = ((unsigned long)(addr1) >> 0x08) & 0xff; \
    frame->src_addr[5] = ((unsigned long)(addr1) >> 0x10) & 0xff; 

#define LENGTH(frame, value) frame->length = value;

#define MAC_HEADER_LEN 6+6+2
#define FRAME_MIN 64

/* MAC Frame struct */
typedef struct MAC_data_frame
{
    u8 des_addr[6];
    u8 src_addr[6];
    union
    {
	u16 length;
	u16 type;
    };
    u8 *data;
}MAC_data_frame;

typedef struct MAC_ctrl_frame
{
    u8 des_addr[6];
    u8 src_addr[6];
    union
    {
	u16 length;
	u16 type;
    };
    u16 opcode;
    u8 *data;
}MAC_ctrl_frame;


static void eth_init();
static void set_frame(MAC_data_frame *frame, u32 len);
static void loop_back_test(MAC_data_frame *frame);
static void fill_rx_db();
static void send_one_normal_frame(MAC_data_frame *frame);
static void wait_for_tx_init();
static  int compare_data(MAC_data_frame *s_frame, MAC_data_frame *r_frame);
static void send_one_huge_frame(MAC_data_frame *frame);
static void send_one_small_frame(MAC_data_frame *frame);
static void wait_for_rx_init();
static void read_rx_normal_frame(MAC_data_frame *frame);
static void send_one_frame(MAC_data_frame *frame, u8 *send_buf);