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📄 ncrreg.h

📁 国产CPU-龙芯(loongson)BIOS源代码
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****	Selection****-----------------------------------------------------------****	SEL_ABS | SCR_ID (0..7)     [ | REL_JMP]**	<<alternate_address>>****	SEL_TBL | << dnad_offset>>  [ | REL_JMP]**	<<alternate_address>>****-----------------------------------------------------------*/#define	SCR_SEL_ABS	0x40000000#define	SCR_SEL_ABS_ATN	0x41000000#define	SCR_SEL_TBL	0x42000000#define	SCR_SEL_TBL_ATN	0x43000000struct scr_tblsel {        u_int8_t  sel_0;        u_int8_t  sel_sxfer;        u_int8_t  sel_id;        u_int8_t  sel_scntl3;};#define SCR_JMP_REL     0x04000000#define SCR_ID(id)	(((u_int32_t)(id)) << 16)/*-----------------------------------------------------------****	Waiting for Disconnect or Reselect****-----------------------------------------------------------****	WAIT_DISC**	dummy: <<alternate_address>>****	WAIT_RESEL**	<<alternate_address>>****-----------------------------------------------------------*/#define	SCR_WAIT_DISC	0x48000000#define SCR_WAIT_RESEL  0x50000000/*-----------------------------------------------------------****	Bit Set / Reset****-----------------------------------------------------------****	SET (flags {|.. })****	CLR (flags {|.. })****-----------------------------------------------------------*/#define SCR_SET(f)     (0x58000000 | (f))#define SCR_CLR(f)     (0x60000000 | (f))#define	SCR_CARRY	0x00000400#define	SCR_TRG		0x00000200#define	SCR_ACK		0x00000040#define	SCR_ATN		0x00000008/*-----------------------------------------------------------****	Memory to memory move****-----------------------------------------------------------****	COPY (bytecount)**	<< source_address >>**	<< destination_address >>****	SCR_COPY   sets the NO FLUSH option by default.**	SCR_COPY_F does not set this option.****	For chips which do not support this option,**	ncr_copy_and_bind() will remove this bit.**-----------------------------------------------------------*/#define SCR_NO_FLUSH 0x01000000#define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n))#define SCR_COPY_F(n) (0xc0000000 | (n))/*-----------------------------------------------------------****	Register move and binary operations****-----------------------------------------------------------****	SFBR_REG (reg, op, data)        reg  = SFBR op data**	<< 0 >>****	REG_SFBR (reg, op, data)        SFBR = reg op data**	<< 0 >>****	REG_REG  (reg, op, data)        reg  = reg op data**	<< 0 >>****-----------------------------------------------------------*/#define SCR_REG_OFS(ofs) ((ofs) << 16ul)#define SCR_SFBR_REG(reg,op,data) \        (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | ((data)<<8ul))#define SCR_REG_SFBR(reg,op,data) \        (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | ((data)<<8ul))#define SCR_REG_REG(reg,op,data) \        (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | ((data)<<8ul))#define      SCR_LOAD   0x00000000#define      SCR_SHL    0x01000000#define      SCR_OR     0x02000000#define      SCR_XOR    0x03000000#define      SCR_AND    0x04000000#define      SCR_SHR    0x05000000#define      SCR_ADD    0x06000000#define      SCR_ADDC   0x07000000/*-----------------------------------------------------------****	FROM_REG (reg)		  reg  = SFBR**	<< 0 >>****	TO_REG	 (reg)		  SFBR = reg**	<< 0 >>****	LOAD_REG (reg, data)	  reg  = <data>**	<< 0 >>****	LOAD_SFBR(data) 	  SFBR = <data>**	<< 0 >>****-----------------------------------------------------------*/#define	SCR_FROM_REG(reg) \	SCR_REG_SFBR(reg,SCR_OR,0)#define	SCR_TO_REG(reg) \	SCR_SFBR_REG(reg,SCR_OR,0)#define	SCR_LOAD_REG(reg,data) \	SCR_REG_REG(reg,SCR_LOAD,data)#define SCR_LOAD_SFBR(data) \        (SCR_REG_SFBR (gpreg, SCR_LOAD, data))/*-----------------------------------------------------------****	Waiting for Disconnect or Reselect****-----------------------------------------------------------****	JUMP            [ | IFTRUE/IFFALSE ( ... ) ]**	<<address>>****	JUMPR           [ | IFTRUE/IFFALSE ( ... ) ]**	<<distance>>****	CALL            [ | IFTRUE/IFFALSE ( ... ) ]**	<<address>>****	CALLR           [ | IFTRUE/IFFALSE ( ... ) ]**	<<distance>>****	RETURN          [ | IFTRUE/IFFALSE ( ... ) ]**	<<dummy>>****	INT             [ | IFTRUE/IFFALSE ( ... ) ]**	<<ident>>****	INT_FLY         [ | IFTRUE/IFFALSE ( ... ) ]**	<<ident>>****	Conditions:**	     WHEN (phase)**	     IF   (phase)**	     CARRY**	     DATA (data, mask)****-----------------------------------------------------------*/#define SCR_NO_OP       0x80000000#define SCR_JUMP        0x80080000#define SCR_JUMPR       0x80880000#define SCR_CALL        0x88080000#define SCR_CALLR       0x88880000#define SCR_RETURN      0x90080000#define SCR_INT         0x98080000#define SCR_INT_FLY     0x98180000#define IFFALSE(arg)   (0x00080000 | (arg))#define IFTRUE(arg)    (0x00000000 | (arg))#define WHEN(phase)    (0x00030000 | (phase))#define IF(phase)      (0x00020000 | (phase))#define DATA(D)        (0x00040000 | ((D) & 0xff))#define MASK(D,M)      (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff))#define CARRYSET       (0x00200000)/*-----------------------------------------------------------****	SCSI  constants.****-----------------------------------------------------------*//***	Messages*/#ifdef __OpenBSD__#include <scsi/scsi_message.h>#define	M_COMPLETE	MSG_CMDCOMPLETE#define	M_EXTENDED	MSG_EXTENDED#define	M_SAVE_DP	MSG_SAVEDATAPOINTER#define	M_RESTORE_DP	MSG_RESTOREPOINTERS#define	M_DISCONNECT	MSG_DISCONNECT#define	M_ID_ERROR	MSG_INITIATOR_DET_ERR#define	M_ABORT		MSG_ABORT#define	M_REJECT	MSG_MESSAGE_REJECT#define	M_NOOP		MSG_NOOP#define	M_PARITY	MSG_PARITY_ERROR#define	M_LCOMPLETE	MSG_LINK_CMD_COMPLETE#define	M_FCOMPLETE	MSG_LINK_CMD_COMPLETEF#define	M_RESET		MSG_BUS_DEV_RESET#define	M_ABORT_TAG	MSG_ABORT_TAG#define	M_CLEAR_QUEUE	MSG_CLEAR_QUEUE#define	M_INIT_REC	MSG_INIT_RECOVERY#define	M_REL_REC	MSG_REL_RECOVERY#define	M_TERMINATE	MSG_TERM_IO_PROC#define	M_SIMPLE_TAG	MSG_SIMPLE_Q_TAG#define	M_HEAD_TAG	MSG_HEAD_OF_Q_TAG#define	M_ORDERED_TAG	MSG_ORDERED_Q_TAG#define	M_IGN_RESIDUE	MSG_IGN_WIDE_RESIDUE#define	M_IDENTIFY   	MSG_IDENTIFY(0, 0)/* #define	M_X_MODIFY_DP	(0x00) */ 	/* XXX what is this? */#define	M_X_SYNC_REQ	MSG_EXT_SDTR#define	M_X_WIDE_REQ	MSG_EXT_WDTR#else#define	M_COMPLETE	(0x00)#define	M_EXTENDED	(0x01)#define	M_SAVE_DP	(0x02)#define	M_RESTORE_DP	(0x03)#define	M_DISCONNECT	(0x04)#define	M_ID_ERROR	(0x05)#define	M_ABORT		(0x06)#define	M_REJECT	(0x07)#define	M_NOOP		(0x08)#define	M_PARITY	(0x09)#define	M_LCOMPLETE	(0x0a)#define	M_FCOMPLETE	(0x0b)#define	M_RESET		(0x0c)#define	M_ABORT_TAG	(0x0d)#define	M_CLEAR_QUEUE	(0x0e)#define	M_INIT_REC	(0x0f)#define	M_REL_REC	(0x10)#define	M_TERMINATE	(0x11)#define	M_SIMPLE_TAG	(0x20)#define	M_HEAD_TAG	(0x21)#define	M_ORDERED_TAG	(0x22)#define	M_IGN_RESIDUE	(0x23)#define	M_IDENTIFY   	(0x80)#define	M_X_MODIFY_DP	(0x00)#define	M_X_SYNC_REQ	(0x01)#define	M_X_WIDE_REQ	(0x03)#endif/***	Status*/#define	S_GOOD		(0x00)#define	S_CHECK_COND	(0x02)#define	S_COND_MET	(0x04)#define	S_BUSY		(0x08)#define	S_INT		(0x10)#define	S_INT_COND_MET	(0x14)#define	S_CONFLICT	(0x18)#define	S_TERMINATED	(0x20)#define	S_QUEUE_FULL	(0x28)#define	S_ILLEGAL	(0xff)#define	S_SENSE		(0x80)/***	Bits defining chip features.**	For now only some of them are used, since we explicitely **	deal with PCI device id and revision id.*/#define FE_LED0		(1<<0)#define FE_WIDE		(1<<1)#define FE_ULTRA	(1<<2)#define FE_ULTRA2	(1<<3)#define FE_DBLR		(1<<4)#define FE_QUAD		(1<<5)#define FE_ERL		(1<<6)#define FE_CLSE		(1<<7)#define FE_WRIE		(1<<8)#define FE_ERMP		(1<<9)#define FE_BOF		(1<<10)#define FE_DFS		(1<<11)#define FE_PFEN		(1<<12)#define FE_LDSTR	(1<<13)#define FE_RAM		(1<<14)#define FE_CLK80	(1<<15)#define FE_DIFF		(1<<16)#define FE_BIOS		(1<<17)#define FE_CACHE_SET	(FE_ERL|FE_CLSE|FE_WRIE|FE_ERMP)#define FE_SCSI_SET	(FE_WIDE|FE_ULTRA|FE_ULTRA2|FE_DBLR|FE_QUAD|F_CLK80)#define FE_SPECIAL_SET	(FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM)#endif /*__NCR_REG_H__*/

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