📄 cc1100.lst
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132 0x2A, // FSCAL2 Frequency synthesizer calibration.
133 0x00, // FSCAL1 Frequency synthesizer calibration.
134 0x11, // FSCAL0 Frequency synthesizer calibration.
135 0x59, // FSTEST Frequency synthesizer calibration.
136 0x81, // TEST2 Various test settings.
137 0x35, // TEST1 Various test settings.
138 0x09, // TEST0 Various test settings.
139 0x0B, // IOCFG2 GDO2 output pin configuration.
140 0x06, // IOCFG0D GDO0 output pin configuration. Refer to SmartRF?Studio User Manual for detailed p
-seudo register explanation.
141
142 0x04, // PKTCTRL1 Packet automation control.
143 0x05, // PKTCTRL0 Packet automation control.
144 0x00, // ADDR Device address.
145 0x0c // PKTLEN Packet length.
146 };
147 */
148
149 // 100k E
150 const RF_SETTINGS rfSettings = {
151 0x00,
152 0x08, // FSCTRL1 Frequency synthesizer control.
153 0x00, // FSCTRL0 Frequency synthesizer control.
154 0x10, // FREQ2 Frequency control word, high byte.
155 0xA7, // FREQ1 Frequency control word, middle byte.
156 0x62, // FREQ0 Frequency control word, low byte.
157 0x5B, // MDMCFG4 Modem configuration.
158 0xF8, // MDMCFG3 Modem configuration.
159 0x03, // MDMCFG2 Modem configuration.
160 0x22, // MDMCFG1 Modem configuration.
161 0xF8, // MDMCFG0 Modem configuration.
162
163 0x00, // CHANNR Channel number.
164 0x47, // DEVIATN Modem deviation setting (when FSK modulation is enabled).
165 0xB6, // FREND1 Front end RX configuration.
166 0x10, // FREND0 Front end RX configuration.
167 0x18, // MCSM0 Main Radio Control State Machine configuration.
168 0x1D, // FOCCFG Frequency Offset Compensation Configuration.
169 0x1C, // BSCFG Bit synchronization Configuration.
170 0xC7, // AGCCTRL2 AGC control.
171 0x00, // AGCCTRL1 AGC control.
172 0xB2, // AGCCTRL0 AGC control.
173
174 0xEA, // FSCAL3 Frequency synthesizer calibration.
175 0x2A, // FSCAL2 Frequency synthesizer calibration.
176 0x00, // FSCAL1 Frequency synthesizer calibration.
C51 COMPILER V8.02 CC1100 01/09/2008 07:37:30 PAGE 4
177 0x11, // FSCAL0 Frequency synthesizer calibration.
178 0x59, // FSTEST Frequency synthesizer calibration.
179 0x81, // TEST2 Various test settings.
180 0x35, // TEST1 Various test settings.
181 0x09, // TEST0 Various test settings.
182 0x0B, // IOCFG2 GDO2 output pin configuration.
183 0x06, // IOCFG0D GDO0 output pin configuration. Refer to SmartRF?Studio User Manual for detailed p
-seudo register explanation.
184
185 0x04, // PKTCTRL1 Packet automation control.
186 0x05, // PKTCTRL0 Packet automation control.
187 0x00, // ADDR Device address.
188 0x0c // PKTLEN Packet length.
189 };
190 //------------------------------------------------------------------------------------------------------
191 // Chipcon
192 // Product = CC1100
193 // Chip version = E
194 // Crystal accuracy = 40 ppm
195 // X-tal frequency = 26 MHz
196 // RF output power = 0 dBm
197 // RX filterbandwidth = 540.000000 kHz
198 // Deviation = 0.000000
199 // Datarate = 250.000000 kbps
200 // Modulation = (7) MSK
201 // Manchester enable = (0) Manchester disabled
202 // RF Frequency = 433.000000 MHz
203 // Channel spacing = 199.951172 kHz
204 // Channel number = 0
205 // Optimization = Sensitivity
206 // Sync mode = (3) 30/32 sync word bits detected
207 // Format of RX/TX data = (0) Normal mode, use FIFOs for RX and TX
208 // CRC operation = (1) CRC calculation in TX and CRC check in RX enabled
209 // Forward Error Correction = (0) FEC disabled
210 // Length configuration = (1) Variable length packets, packet length configured by the first received byte
- after sync word.
211 // Packetlength = 255
212 // Preamble count = (2) 4 bytes
213 // Append status = 1
214 // Address check = (11) No address check
215 // FIFO autoflush = 0
216 // Device address = 0
217 // GDO0 signal selection = ( 6) Asserts when sync word has been sent / received, and de-asserts at the end
- of the packet
218 // GDO2 signal selection = (11) Serial Clock
219 /*
220 const RF_SETTINGS rfSettings = {
221 0x00,
222
223 0x0B, // FSCTRL1 Frequency synthesizer control.
224 0x00, // FSCTRL0 Frequency synthesizer control.
225 0x10, // FREQ2 Frequency control word, high byte.
226 0xA7, // FREQ1 Frequency control word, middle byte.
227 0x62, // FREQ0 Frequency control word, low byte.
228 //250k
229 0x2D, // MDMCFG4 Modem configuration.
230 0x3B, // MDMCFG3 Modem configuration.
231 0x73, // MDMCFG2 Modem configuration.
232 0x22, // MDMCFG1 Modem configuration.
233 0xF8, // MDMCFG0 Modem configuration.
234
235 // 1.2k
C51 COMPILER V8.02 CC1100 01/09/2008 07:37:30 PAGE 5
236 0xF5, //MDMCFG4 (x)
237 0x83, //MDMCFG3 (x)
238 0x03, //MDMCFG2 (x)
239 0x22, //MDMCFG1 (x)
240 0xF8, //MDMCFG0 (x)
241
242 0x00, // CHANNR Channel number.
243
244 //0x00, // DEVIATN Modem deviation setting (when FSK modulation is enabled).
245 0x15, //DEVIATN (x)
246 0xB6, // FREND1 Front end RX configuration.
247 0x10, // FREND0 Front end RX configuration.
248 0x18, // MCSM0 Main Radio Control State Machine configuration.
249 0x1D, // FOCCFG Frequency Offset Compensation Configuration.
250 0x1C, // BSCFG Bit synchronization Configuration.
251 0xC7, // AGCCTRL2 AGC control.
252 0x00, // AGCCTRL1 AGC control.
253 0xB2, // AGCCTRL0 AGC control.
254
255 0xEA, // FSCAL3 Frequency synthesizer calibration.
256 0x0A, // FSCAL2 Frequency synthesizer calibration.
257 0x00, // FSCAL1 Frequency synthesizer calibration.
258 0x11, // FSCAL0 Frequency synthesizer calibration.
259 0x59, // FSTEST Frequency synthesizer calibration.
260 0x88, // TEST2 Various test settings.
261 0x31, // TEST1 Various test settings.
262 0x0B, // TEST0 Various test settings.
263 0x0B, // IOCFG2 GDO2 output pin configuration.
264 0x06, // IOCFG0D GDO0 output pin configuration. Refer to SmartRF?Studio User Manual for detailed p
-seudo register explanation.
265
266 0x04, // PKTCTRL1 Packet automation control.
267 //0x05, // PKTCTRL1 Packet automation control. //地址检测
268 0x45, // PKTCTRL0 Packet automation control. //可变长数据包,通过同步词汇后的第一个位置配置数据包长⌨️ 快捷键说明
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