📄 mixframea.lst
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0098.4 +1 161 REN BIT SCON.4 ; RECEIVE ENABLE
0098.5 +1 162 SM2 BIT SCON.5 ; MULTIPROCESSOR COMMUNICATION ENABLE
0098.6 +1 163 SM1 BIT SCON.6 ; SERIAL MODE CONTROL BIT 1
0098.7 +1 164 SM0 BIT SCON.7 ; SERIAL MODE CONTROL BIT 0
+1 165 ;
+1 166 ; IE A8H
00A8.0 +1 167 EX0 BIT IE.0 ; EXTERNAL INTERRUPT 0 ENABLE
00A8.1 +1 168 ET0 BIT IE.1 ; TIMER 0 INTERRUPT ENABLE
00A8.2 +1 169 EX1 BIT IE.2 ; EXTERNAL INTERRUPT 1 ENABLE
00A8.3 +1 170 ET1 BIT IE.3 ; TIMER 1 INTERRUPT ENABLE
00A8.4 +1 171 ES BIT IE.4 ; SERIAL PORT INTERRUPT ENABLE
00A8.5 +1 172 ET2 BIT IE.5 ; TIMER 2 INTERRUPT ENABLE
00A8.7 +1 173 EA BIT IE.7 ; GLOBAL INTERRUPT ENABLE
+1 174 ;
+1 175 ; IP B8H
00B8.0 +1 176 PX0 BIT IP.0 ; EXTERNAL INTERRUPT 0 PRIORITY
00B8.1 +1 177 PT0 BIT IP.1 ; TIMER 0 PRIORITY
00B8.2 +1 178 PX1 BIT IP.2 ; EXTERNAL INTERRUPT 1 PRIORITY
00B8.3 +1 179 PT1 BIT IP.3 ; TIMER 1 PRIORITY
00B8.4 +1 180 PS BIT IP.4 ; SERIAL PORT PRIORITY
00B8.5 +1 181 PT2 BIT IP.5 ; TIMER 2 PRIORITY
+1 182 ;
+1 183 ; SMB0CN C0H
00C0.0 +1 184 SMBTOE BIT SMB0CN.0 ; SMBUS 0 TIMEOUT ENABLE
00C0.1 +1 185 SMBFTE BIT SMB0CN.1 ; SMBUS 0 FREE TIMER ENABLE
00C0.2 +1 186 AA BIT SMB0CN.2 ; SMBUS 0 ASSERT/ACKNOWLEDGE FLAG
00C0.3 +1 187 SI BIT SMB0CN.3 ; SMBUS 0 INTERRUPT PENDING FLAG
00C0.4 +1 188 STO BIT SMB0CN.4 ; SMBUS 0 STOP FLAG
00C0.5 +1 189 STA BIT SMB0CN.5 ; SMBUS 0 START FLAG
00C0.6 +1 190 ENSMB BIT SMB0CN.6 ; SMBUS 0 ENABLE
AX51 MACRO ASSEMBLER MIXFRAMEA 06/13/06 10:15:31 PAGE 4
+1 191 ;
+1 192 ; T2CON C8H
00C8.0 +1 193 CPRL2 BIT T2CON.0 ; CAPTURE OR RELOAD SELECT
00C8.1 +1 194 CT2 BIT T2CON.1 ; TIMER OR COUNTER SELECT
00C8.2 +1 195 TR2 BIT T2CON.2 ; TIMER 2 ON/OFF CONTROL
00C8.3 +1 196 EXEN2 BIT T2CON.3 ; TIMER 2 EXTERNAL ENABLE FLAG
00C8.4 +1 197 TCLK BIT T2CON.4 ; TRANSMIT CLOCK FLAG
00C8.5 +1 198 RCLK BIT T2CON.5 ; RECEIVE CLOCK FLAG
00C8.6 +1 199 EXF2 BIT T2CON.6 ; EXTERNAL FLAG
00C8.7 +1 200 TF2 BIT T2CON.7 ; TIMER 2 OVERFLOW FLAG
+1 201 ;
+1 202 ; PSW D0H
00D0.0 +1 203 P BIT PSW.0 ; ACCUMULATOR PARITY FLAG
00D0.1 +1 204 F1 BIT PSW.1 ; USER FLAG 1
00D0.2 +1 205 OV BIT PSW.2 ; OVERFLOW FLAG
00D0.3 +1 206 RS0 BIT PSW.3 ; REGISTER BANK SELECT 0
00D0.4 +1 207 RS1 BIT PSW.4 ; REGISTER BANK SELECT 1
00D0.5 +1 208 F0 BIT PSW.5 ; USER FLAG 0
00D0.6 +1 209 AC BIT PSW.6 ; AUXILIARY CARRY FLAG
00D0.7 +1 210 CY BIT PSW.7 ; CARRY FLAG
+1 211 ;
+1 212 ; PCA0CN D8H
00D8.0 +1 213 CCF0 BIT PCA0CN.0 ; PCA 0 MODULE 0 INTERRUPT FLAG
00D8.1 +1 214 CCF1 BIT PCA0CN.1 ; PCA 0 MODULE 1 INTERRUPT FLAG
00D8.2 +1 215 CCF2 BIT PCA0CN.2 ; PCA 0 MODULE 2 INTERRUPT FLAG
00D8.3 +1 216 CCF3 BIT PCA0CN.3 ; PCA 0 MODULE 3 INTERRUPT FLAG
00D8.4 +1 217 CCF4 BIT PCA0CN.4 ; PCA 0 MODULE 4 INTERRUPT FLAG
00D8.6 +1 218 CR BIT PCA0CN.6 ; PCA 0 COUNTER RUN CONTROL BIT
00D8.7 +1 219 CF BIT PCA0CN.7 ; PCA 0 COUNTER OVERFLOW FLAG
+1 220 ;
+1 221 ; ADC0CN E8H
00E8.0 +1 222 ADLJST BIT ADC0CN.0 ; ADC 0 RIGHT JUSTIFY DATA BIT
00E8.1 +1 223 ADWINT BIT ADC0CN.1 ; ADC 0 WINDOW COMPARE INTERRUPT FLAG
00E8.2 +1 224 ADSTM0 BIT ADC0CN.2 ; ADC 0 START OF CONVERSION MODE BIT 0
00E8.3 +1 225 ADSTM1 BIT ADC0CN.3 ; ADC 0 START OF CONVERSION MODE BIT 1
00E8.4 +1 226 ADBUSY BIT ADC0CN.4 ; ADC 0 BUSY FLAG
00E8.5 +1 227 ADCINT BIT ADC0CN.5 ; ADC 0 CONVERISION COMPLETE INTERRUPT FLAG
00E8.6 +1 228 ADCTM BIT ADC0CN.6 ; ADC 0 TRACK MODE
00E8.7 +1 229 ADCEN BIT ADC0CN.7 ; ADC 0 ENABLE
+1 230 ;
+1 231 ; SPI0CN F8H
00F8.0 +1 232 SPIEN BIT SPI0CN.0 ; SPI 0 SPI ENABLE
00F8.1 +1 233 MSTEN BIT SPI0CN.1 ; SPI 0 MASTER ENABLE
00F8.2 +1 234 SLVSEL BIT SPI0CN.2 ; SPI 0 SLAVE SELECT
00F8.3 +1 235 TXBSY BIT SPI0CN.3 ; SPI 0 TX BUSY FLAG
00F8.4 +1 236 RXOVRN BIT SPI0CN.4 ; SPI 0 RX OVERRUN FLAG
00F8.5 +1 237 MODF BIT SPI0CN.5 ; SPI 0 MODE FAULT FLAG
00F8.6 +1 238 WCOL BIT SPI0CN.6 ; SPI 0 WRITE COLLISION FLAG
00F8.7 +1 239 SPIF BIT SPI0CN.7 ; SPI 0 INTERRUPT FLAG
240
241 ;=================================
242 name DNLD_SUB
------ 243 dnldcseg SEGMENT CODE ;our code segment
244 ;=================================
245 ; New IRAM(80-FF) Variable definition for New board
246 ;---------------------------------
000020 247 DSEG at 20h
000020 248 AsmArg: ds 2 ;int defined in ASM
249
250 ;=========================================
------ 251 rseg dnldcseg ;use our own code segment
252 ;=========================================
253 ; Data initialization for startup
254 ;-----------------------------------------
000000 255 DataInit: ;original L287D
256
AX51 MACRO ASSEMBLER MIXFRAMEA 06/13/06 10:15:31 PAGE 5
000000 750003 E 257 mov CArg,#3
000003 22 258 ret
259 ;==========================
260 ; UART INT routine
261 ;--------------------------
000004 262 UartInt:
000004 C0E0 263 PUSH ACC
000006 C083 264 PUSH DPH
000008 C082 265 PUSH DPL
00000A C0D0 266 PUSH PSW
267
268 ;add your codes here
269
00000C D0D0 270 POP PSW
00000E D082 271 POP DPL
000010 D083 272 POP DPH
000012 D0E0 273 POP ACC
000014 32 274 RETI
275 ;---------------------
276 ;==========================
277 ; Timer0 INT,excutew every 10ms
278 ;--------------------------
000015 279 Timer0Int:
000015 C0E0 280 PUSH ACC ;2T
000017 C0F0 281 PUSH B ;2T
000019 C083 282 PUSH DPH ;2T
00001B C082 283 PUSH DPL ;2T
00001D C0D0 284 PUSH PSW ;2T
00001F 75D008 285 MOV PSW,#8 ;3T
000022 C28C 286 CLR TR0 ;2T,Total=15T
287
288 ;add your codes here
289
000024 D0D0 290 POP PSW
000026 D082 291 POP DPL
000028 D083 292 POP DPH
00002A D0F0 293 POP B
00002C D0E0 294 POP ACC
00002E 32 295 RETI
296 ;=====================
297 END
AX51 MACRO ASSEMBLER MIXFRAMEA 06/13/06 10:15:31 PAGE 6
SYMBOL TABLE LISTING
------ ----- -------
N A M E T Y P E V A L U E ATTRIBUTES
?C_STARTUP . . . . . . . C ADDR ------- EXT
AA . . . . . . . . . . . B ADDR 00C0H.2 A
AC . . . . . . . . . . . B ADDR 00D0H.6 A
ACC. . . . . . . . . . . D ADDR 00E0H A
ADBUSY . . . . . . . . . B ADDR 00E8H.4 A
ADC0CF . . . . . . . . . D ADDR 00BCH A
ADC0CN . . . . . . . . . D ADDR 00E8H A
ADC0GTH. . . . . . . . . D ADDR 00C5H A
ADC0GTL. . . . . . . . . D ADDR 00C4H A
ADC0H. . . . . . . . . . D ADDR 00BFH A
ADC0L. . . . . . . . . . D ADDR 00BEH A
ADC0LTH. . . . . . . . . D ADDR 00C7H A
ADC0LTL. . . . . . . . . D ADDR 00C6H A
ADCEN. . . . . . . . . . B ADDR 00E8H.7 A
ADCINT . . . . . . . . . B ADDR 00E8H.5 A
ADCTM. . . . . . . . . . B ADDR 00E8H.6 A
ADLJST . . . . . . . . . B ADDR 00E8H.0 A
ADSTM0 . . . . . . . . . B ADDR 00E8H.2 A
ADSTM1 . . . . . . . . . B ADDR 00E8H.3 A
ADWINT . . . . . . . . . B ADDR 00E8H.1 A
AMX0CF . . . . . . . . . D ADDR 00BAH A
AMX0SL . . . . . . . . . D ADDR 00BBH A
ASMARG . . . . . . . . . D ADDR 0020H R SEG=?DT?MIXFRAMEA?2
B. . . . . . . . . . . . D ADDR 00F0H A
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