📄 startup.lst
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AX51 MACRO ASSEMBLER STARTUP 06/13/06 10:15:30 PAGE 1
MACRO ASSEMBLER AX51 V2.14
OBJECT MODULE PLACED IN STARTUP.OBJ
ASSEMBLER INVOKED BY: e:\Keil\C51\BIN\AX51.EXE STARTUP.A51 SET(SMALL) DEBUG EP
LOC OBJ LINE SOURCE
1 ;*****************************************
2 ; StartUp initialization file STARTUP.A51 for C&ASM mix programing
3 ;-----------------------------------------
4 $nomod51
5 ;$include (C8051F000.inc)
+1 6 ;-----------------------------------------------------------------------------
+1 7 ; Copyright (C) 2000 CYGNAL INTEGRATED PRODUCTS, INC.
+1 8 ; All rights reserved.
+1 9 ;
+1 10 ;
+1 11 ; FILE NAME : C8051F000.INC
+1 12 ; TARGET MCU : C8051F0xx (C8051 System Controller)
+1 13 ; DESCRIPTION : Register/bit definitions for the C8051F000 product family.
+1 14 ;
+1 15 ; REVISION 1.8
+1 16 ;
+1 17 ;-----------------------------------------------------------------------------
+1 18 ;REGISTER DEFINITIONS
+1 19 ;
0080 +1 20 P0 DATA 080H ; PORT 0
0081 +1 21 SP DATA 081H ; STACK POINTER
0082 +1 22 DPL DATA 082H ; DATA POINTER - LOW BYTE
0083 +1 23 DPH DATA 083H ; DATA POINTER - HIGH BYTE
0087 +1 24 PCON DATA 087H ; POWER CONTROL
0088 +1 25 TCON DATA 088H ; TIMER CONTROL
0089 +1 26 TMOD DATA 089H ; TIMER MODE
008A +1 27 TL0 DATA 08AH ; TIMER 0 - LOW BYTE
008B +1 28 TL1 DATA 08BH ; TIMER 1 - LOW BYTE
008C +1 29 TH0 DATA 08CH ; TIMER 0 - HIGH BYTE
008D +1 30 TH1 DATA 08DH ; TIMER 1 - HIGH BYTE
008E +1 31 CKCON DATA 08EH ; CLOCK CONTROL
008F +1 32 PSCTL DATA 08FH ; PROGRAM STORE R/W CONTROL
0090 +1 33 P1 DATA 090H ; PORT 1
0091 +1 34 TMR3CN DATA 091H ; TIMER 3 CONTROL
0092 +1 35 TMR3RLL DATA 092H ; TIMER 3 RELOAD REGISTER - LOW BYTE
0093 +1 36 TMR3RLH DATA 093H ; TIMER 3 RELOAD REGISTER - HIGH BYTE
0094 +1 37 TMR3L DATA 094H ; TIMER 3 - LOW BYTE
0095 +1 38 TMR3H DATA 095H ; TIMER 3 - HIGH BYTE
0097 +1 39 DSRFLG DATA 097H ; DSR FLAG REGISTER
0098 +1 40 SCON DATA 098H ; SERIAL PORT CONTROL
0099 +1 41 SBUF DATA 099H ; SERIAL PORT BUFFER
009A +1 42 SPI0CFG DATA 09AH ; SERIAL PERIPHERAL INTERFACE 0 CONFIGURATION
009B +1 43 SPI0DAT DATA 09BH ; SERIAL PERIPHERAL INTERFACE 0 DATA
009D +1 44 SPI0CKR DATA 09DH ; SERIAL PERIPHERAL INTERFACE 0 CLOCK RATE CONTROL
009E +1 45 CPT0CN DATA 09EH ; COMPARATOR 0 CONTROL
009F +1 46 CPT1CN DATA 09FH ; COMPARATOR 1 CONTROL
00A0 +1 47 P2 DATA 0A0H ; PORT 2
00A4 +1 48 PRT0CF DATA 0A4H ; PORT 0 CONFIGURATION
00A5 +1 49 PRT1CF DATA 0A5H ; PORT 1 CONFIGURATION
00A6 +1 50 PRT2CF DATA 0A6H ; PORT 2 CONFIGURATION
00A7 +1 51 PRT3CF DATA 0A7H ; PORT 3 CONFIGURATION
00A8 +1 52 IE DATA 0A8H ; INTERRUPT ENABLE
00AD +1 53 PRT1IF DATA 0ADH ; PORT 1 EXTERNAL INTERRUPT FLAGS
00AF +1 54 EMI0CN DATA 0AFH ; EXTERNAL MEMORY INTERFACE CONTROL
00B0 +1 55 P3 DATA 0B0H ; PORT 3
00B1 +1 56 OSCXCN DATA 0B1H ; EXTERNAL OSCILLATOR CONTROL
00B2 +1 57 OSCICN DATA 0B2H ; INTERNAL OSCILLATOR CONTROL
00B3 +1 58 DSRL DATA 0B3H ; DSR PORT - LOW BYTE
AX51 MACRO ASSEMBLER STARTUP 06/13/06 10:15:30 PAGE 2
00B4 +1 59 DSRH DATA 0B4H ; DSR PORT - HIGH BYTE
00B6 +1 60 FLSCL DATA 0B6H ; FLASH MEMORY TIMING PRESCALER
00B7 +1 61 FLACL DATA 0B7H ; FLASH ACESS LIMIT
00B8 +1 62 IP DATA 0B8H ; INTERRUPT PRIORITY
00BA +1 63 AMX0CF DATA 0BAH ; ADC 0 MUX CONFIGURATION
00BB +1 64 AMX0SL DATA 0BBH ; ADC 0 MUX CHANNEL SELECTION
00BC +1 65 ADC0CF DATA 0BCH ; ADC 0 CONFIGURATION
00BE +1 66 ADC0L DATA 0BEH ; ADC 0 DATA - LOW BYTE
00BF +1 67 ADC0H DATA 0BFH ; ADC 0 DATA - HIGH BYTE
00C0 +1 68 SMB0CN DATA 0C0H ; SMBUS 0 CONTROL
00C1 +1 69 SMB0STA DATA 0C1H ; SMBUS 0 STATUS
00C2 +1 70 SMB0DAT DATA 0C2H ; SMBUS 0 DATA
00C3 +1 71 SMB0ADR DATA 0C3H ; SMBUS 0 SLAVE ADDRESS
00C4 +1 72 ADC0GTL DATA 0C4H ; ADC 0 GREATER-THAN REGISTER - LOW BYTE
00C5 +1 73 ADC0GTH DATA 0C5H ; ADC 0 GREATER-THAN REGISTER - HIGH BYTE
00C6 +1 74 ADC0LTL DATA 0C6H ; ADC 0 LESS-THAN REGISTER - LOW BYTE
00C7 +1 75 ADC0LTH DATA 0C7H ; ADC 0 LESS-THAN REGISTER - HIGH BYTE
00C8 +1 76 T2CON DATA 0C8H ; TIMER 2 CONTROL
00CA +1 77 RCAP2L DATA 0CAH ; TIMER 2 CAPTURE REGISTER - LOW BYTE
00CB +1 78 RCAP2H DATA 0CBH ; TIMER 2 CAPTURE REGISTER - HIGH BYTE
00CC +1 79 TL2 DATA 0CCH ; TIMER 2 - LOW BYTE
00CD +1 80 TH2 DATA 0CDH ; TIMER 2 - HIGH BYTE
00CE +1 81 DSROP DATA 0CEH ; DSR OPERAND
00CF +1 82 SMB0CR DATA 0CFH ; SMBUS 0 CLOCK RATE
00D0 +1 83 PSW DATA 0D0H ; PROGRAM STATUS WORD
00D1 +1 84 REF0CN DATA 0D1H ; VOLTAGE REFERENCE 0 CONTROL
00D2 +1 85 DAC0L DATA 0D2H ; DAC 0 REGISTER - LOW BYTE
00D3 +1 86 DAC0H DATA 0D3H ; DAC 0 REGISTER - HIGH BYTE
00D4 +1 87 DAC0CN DATA 0D4H ; DAC 0 CONTROL
00D5 +1 88 DAC1L DATA 0D5H ; DAC 1 REGISTER - LOW BYTE
00D6 +1 89 DAC1H DATA 0D6H ; DAC 1 REGISTER - HIGH BYTE
00D7 +1 90 DAC1CN DATA 0D7H ; DAC 1 CONTROL
00D8 +1 91 PCA0CN DATA 0D8H ; PCA 0 COUNTER CONTROL
00D9 +1 92 PCA0MD DATA 0D9H ; PCA 0 COUNTER MODE
00DA +1 93 PCA0CPM0 DATA 0DAH ; CONTROL REGISTER FOR PCA 0 MODULE 0
00DB +1 94 PCA0CPM1 DATA 0DBH ; CONTROL REGISTER FOR PCA 0 MODULE 1
00DC +1 95 PCA0CPM2 DATA 0DCH ; CONTROL REGISTER FOR PCA 0 MODULE 2
00DD +1 96 PCA0CPM3 DATA 0DDH ; CONTROL REGISTER FOR PCA 0 MODULE 3
00DE +1 97 PCA0CPM4 DATA 0DEH ; CONTROL REGISTER FOR PCA 0 MODULE 4
00E0 +1 98 ACC DATA 0E0H ; ACCUMULATOR
00E1 +1 99 XBR0 DATA 0E1H ; DIGITAL CROSSBAR CONFIGURATION REGISTER 0
00E2 +1 100 XBR1 DATA 0E2H ; DIGITAL CROSSBAR CONFIGURATION REGISTER 1
00E3 +1 101 XBR2 DATA 0E3H ; DIGITAL CROSSBAR CONFIGURATION REGISTER 2
00E6 +1 102 EIE1 DATA 0E6H ; EXTERNAL INTERRUPT ENABLE 1
00E7 +1 103 EIE2 DATA 0E7H ; EXTERNAL INTERRUPT ENABLE 2
00E8 +1 104 ADC0CN DATA 0E8H ; ADC 0 CONTROL
00E9 +1 105 PCA0L DATA 0E9H ; PCA 0 TIMER - LOW BYTE
00EA +1 106 PCA0CPL0 DATA 0EAH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - LOW BYTE
00EB +1 107 PCA0CPL1 DATA 0EBH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - LOW BYTE
00EC +1 108 PCA0CPL2 DATA 0ECH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - LOW BYTE
00ED +1 109 PCA0CPL3 DATA 0EDH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - LOW BYTE
00EE +1 110 PCA0CPL4 DATA 0EEH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - LOW BYTE
00EF +1 111 RSTSRC DATA 0EFH ; RESET SOURCE
00F0 +1 112 B DATA 0F0H ; B REGISTER
00F6 +1 113 EIP1 DATA 0F6H ; EXTERNAL INTERRUPT PRIORITY REGISTER 1
00F7 +1 114 EIP2 DATA 0F7H ; EXTERNAL INTERRUPT PRIORITY REGISTER 2
00F8 +1 115 SPI0CN DATA 0F8H ; SERIAL PERIPHERAL INTERFACE 0 CONTROL
00F9 +1 116 PCA0H DATA 0F9H ; PCA 0 TIMER - HIGH BYTE
00FA +1 117 PCA0CPH0 DATA 0FAH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - HIGH BYTE
00FB +1 118 PCA0CPH1 DATA 0FBH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - HIGH BYTE
00FC +1 119 PCA0CPH2 DATA 0FCH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - HIGH BYTE
00FD +1 120 PCA0CPH3 DATA 0FDH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - HIGH BYTE
00FE +1 121 PCA0CPH4 DATA 0FEH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - HIGH BYTE
00FF +1 122 WDTCN DATA 0FFH ; WATCHDOG TIMER CONTROL
+1 123 ;
+1 124 ;------------------------------------------------------------------------------
AX51 MACRO ASSEMBLER STARTUP 06/13/06 10:15:30 PAGE 3
+1 125 ;BIT DEFINITIONS
+1 126 ;
+1 127 ; TCON 88H
0088.0 +1 128 IT0 BIT TCON.0 ; EXT. INTERRUPT 0 TYPE
0088.1 +1 129 IE0 BIT TCON.1 ; EXT. INTERRUPT 0 EDGE FLAG
0088.2 +1 130 IT1 BIT TCON.2 ; EXT. INTERRUPT 1 TYPE
0088.3 +1 131 IE1 BIT TCON.3 ; EXT. INTERRUPT 1 EDGE FLAG
0088.4 +1 132 TR0 BIT TCON.4 ; TIMER 0 ON/OFF CONTROL
0088.5 +1 133 TF0 BIT TCON.5 ; TIMER 0 OVERFLOW FLAG
0088.6 +1 134 TR1 BIT TCON.6 ; TIMER 1 ON/OFF CONTROL
0088.7 +1 135 TF1 BIT TCON.7 ; TIMER 1 OVERFLOW FLAG
+1 136 ;
+1 137 ; SCON 98H
0098.0 +1 138 RI BIT SCON.0 ; RECEIVE INTERRUPT FLAG
0098.1 +1 139 TI BIT SCON.1 ; TRANSMIT INTERRUPT FLAG
0098.2 +1 140 RB8 BIT SCON.2 ; RECEIVE BIT 8
0098.3 +1 141 TB8 BIT SCON.3 ; TRANSMIT BIT 8
0098.4 +1 142 REN BIT SCON.4 ; RECEIVE ENABLE
0098.5 +1 143 SM2 BIT SCON.5 ; MULTIPROCESSOR COMMUNICATION ENABLE
0098.6 +1 144 SM1 BIT SCON.6 ; SERIAL MODE CONTROL BIT 1
0098.7 +1 145 SM0 BIT SCON.7 ; SERIAL MODE CONTROL BIT 0
+1 146 ;
+1 147 ; IE A8H
00A8.0 +1 148 EX0 BIT IE.0 ; EXTERNAL INTERRUPT 0 ENABLE
00A8.1 +1 149 ET0 BIT IE.1 ; TIMER 0 INTERRUPT ENABLE
00A8.2 +1 150 EX1 BIT IE.2 ; EXTERNAL INTERRUPT 1 ENABLE
00A8.3 +1 151 ET1 BIT IE.3 ; TIMER 1 INTERRUPT ENABLE
00A8.4 +1 152 ES BIT IE.4 ; SERIAL PORT INTERRUPT ENABLE
00A8.5 +1 153 ET2 BIT IE.5 ; TIMER 2 INTERRUPT ENABLE
00A8.7 +1 154 EA BIT IE.7 ; GLOBAL INTERRUPT ENABLE
+1 155 ;
+1 156 ; IP B8H
00B8.0 +1 157 PX0 BIT IP.0 ; EXTERNAL INTERRUPT 0 PRIORITY
00B8.1 +1 158 PT0 BIT IP.1 ; TIMER 0 PRIORITY
00B8.2 +1 159 PX1 BIT IP.2 ; EXTERNAL INTERRUPT 1 PRIORITY
00B8.3 +1 160 PT1 BIT IP.3 ; TIMER 1 PRIORITY
00B8.4 +1 161 PS BIT IP.4 ; SERIAL PORT PRIORITY
00B8.5 +1 162 PT2 BIT IP.5 ; TIMER 2 PRIORITY
+1 163 ;
+1 164 ; SMB0CN C0H
00C0.0 +1 165 SMBTOE BIT SMB0CN.0 ; SMBUS 0 TIMEOUT ENABLE
00C0.1 +1 166 SMBFTE BIT SMB0CN.1 ; SMBUS 0 FREE TIMER ENABLE
00C0.2 +1 167 AA BIT SMB0CN.2 ; SMBUS 0 ASSERT/ACKNOWLEDGE FLAG
00C0.3 +1 168 SI BIT SMB0CN.3 ; SMBUS 0 INTERRUPT PENDING FLAG
00C0.4 +1 169 STO BIT SMB0CN.4 ; SMBUS 0 STOP FLAG
00C0.5 +1 170 STA BIT SMB0CN.5 ; SMBUS 0 START FLAG
00C0.6 +1 171 ENSMB BIT SMB0CN.6 ; SMBUS 0 ENABLE
+1 172 ;
+1 173 ; T2CON C8H
00C8.0 +1 174 CPRL2 BIT T2CON.0 ; CAPTURE OR RELOAD SELECT
00C8.1 +1 175 CT2 BIT T2CON.1 ; TIMER OR COUNTER SELECT
00C8.2 +1 176 TR2 BIT T2CON.2 ; TIMER 2 ON/OFF CONTROL
00C8.3 +1 177 EXEN2 BIT T2CON.3 ; TIMER 2 EXTERNAL ENABLE FLAG
00C8.4 +1 178 TCLK BIT T2CON.4 ; TRANSMIT CLOCK FLAG
00C8.5 +1 179 RCLK BIT T2CON.5 ; RECEIVE CLOCK FLAG
00C8.6 +1 180 EXF2 BIT T2CON.6 ; EXTERNAL FLAG
00C8.7 +1 181 TF2 BIT T2CON.7 ; TIMER 2 OVERFLOW FLAG
+1 182 ;
+1 183 ; PSW D0H
00D0.0 +1 184 P BIT PSW.0 ; ACCUMULATOR PARITY FLAG
00D0.1 +1 185 F1 BIT PSW.1 ; USER FLAG 1
00D0.2 +1 186 OV BIT PSW.2 ; OVERFLOW FLAG
00D0.3 +1 187 RS0 BIT PSW.3 ; REGISTER BANK SELECT 0
00D0.4 +1 188 RS1 BIT PSW.4 ; REGISTER BANK SELECT 1
00D0.5 +1 189 F0 BIT PSW.5 ; USER FLAG 0
00D0.6 +1 190 AC BIT PSW.6 ; AUXILIARY CARRY FLAG
AX51 MACRO ASSEMBLER STARTUP 06/13/06 10:15:30 PAGE 4
00D0.7 +1 191 CY BIT PSW.7 ; CARRY FLAG
+1 192 ;
+1 193 ; PCA0CN D8H
00D8.0 +1 194 CCF0 BIT PCA0CN.0 ; PCA 0 MODULE 0 INTERRUPT FLAG
00D8.1 +1 195 CCF1 BIT PCA0CN.1 ; PCA 0 MODULE 1 INTERRUPT FLAG
00D8.2 +1 196 CCF2 BIT PCA0CN.2 ; PCA 0 MODULE 2 INTERRUPT FLAG
00D8.3 +1 197 CCF3 BIT PCA0CN.3 ; PCA 0 MODULE 3 INTERRUPT FLAG
00D8.4 +1 198 CCF4 BIT PCA0CN.4 ; PCA 0 MODULE 4 INTERRUPT FLAG
00D8.6 +1 199 CR BIT PCA0CN.6 ; PCA 0 COUNTER RUN CONTROL BIT
00D8.7 +1 200 CF BIT PCA0CN.7 ; PCA 0 COUNTER OVERFLOW FLAG
+1 201 ;
+1 202 ; ADC0CN E8H
00E8.0 +1 203 ADLJST BIT ADC0CN.0 ; ADC 0 RIGHT JUSTIFY DATA BIT
00E8.1 +1 204 ADWINT BIT ADC0CN.1 ; ADC 0 WINDOW COMPARE INTERRUPT FLAG
00E8.2 +1 205 ADSTM0 BIT ADC0CN.2 ; ADC 0 START OF CONVERSION MODE BIT 0
00E8.3 +1 206 ADSTM1 BIT ADC0CN.3 ; ADC 0 START OF CONVERSION MODE BIT 1
00E8.4 +1 207 ADBUSY BIT ADC0CN.4 ; ADC 0 BUSY FLAG
00E8.5 +1 208 ADCINT BIT ADC0CN.5 ; ADC 0 CONVERISION COMPLETE INTERRUPT FLAG
00E8.6 +1 209 ADCTM BIT ADC0CN.6 ; ADC 0 TRACK MODE
00E8.7 +1 210 ADCEN BIT ADC0CN.7 ; ADC 0 ENABLE
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