example_2833xmcbsp_dlb_dma.c

TI公司TMS320F2883x浮点DSP的详细应用例程

    McbspaRegs.RCR2.all=0x0;			// Single-phase frame, 1 word/frame, No companding	(Receive)
    McbspaRegs.RCR1.all=0x0;

    McbspaRegs.XCR2.all=0x0;			// Single-phase frame, 1 word/frame, No companding	(Transmit)
    McbspaRegs.XCR1.all=0x0;

    McbspaRegs.SRGR2.bit.CLKSM = 1;		// CLKSM=1 (If SCLKME=0, i/p clock to SRG is LSPCLK)
	McbspaRegs.SRGR2.bit.FPER = 31;		// FPER = 32 CLKG periods

    McbspaRegs.SRGR1.bit.FWID = 0;      // Frame Width = 1 CLKG period
    McbspaRegs.SRGR1.bit.CLKGDV = 0;	// CLKG frequency = LSPCLK/(CLKGDV+1)

    McbspaRegs.PCR.bit.FSXM = 1;		// FSX generated internally, FSR derived from an external source
	McbspaRegs.PCR.bit.CLKXM = 1;		// CLKX generated internally, CLKR derived from an external source



    //*************** Initialize McBSP Data Length
    if(WORD_SIZE == 8)             // Run a loopback test in 8-bit mode
    {
      InitMcbspa8bit();
    }
    if(WORD_SIZE == 16)            // Run a loopback test in 16-bit mode
    {
      InitMcbspa16bit();
    }
    if(WORD_SIZE == 32)            // Run a loopback test in 32-bit mode
    {
      InitMcbspa32bit();
    }

    //************* Enable Sample rate generator
    McbspaRegs.SPCR2.bit.GRST=1; // Enable the sample rate generator
    delay_loop();                // Wait at least 2 SRG clock cycles
    McbspaRegs.SPCR2.bit.XRST=1; // Release TX from Reset
    McbspaRegs.SPCR1.bit.RRST=1; // Release RX from Reset
    McbspaRegs.SPCR2.bit.FRST=1; // Frame Sync Generator reset
}

// DMA Initialization for data size <= 16-bit

void init_dma()
{
  EALLOW;
  DmaRegs.DMACTRL.bit.HARDRESET = 1;
  asm(" NOP");						   // Only 1 NOP needed per Design
  DmaRegs.CH1.MODE.bit.CHINTE = 0;
  // Channel 1, McBSPA transmit
  DmaRegs.CH1.BURST_SIZE.all = 0;		// 1 word/burst
  DmaRegs.CH1.SRC_BURST_STEP = 0;		// no effect when using 1 word/burst
  DmaRegs.CH1.DST_BURST_STEP = 0;		// no effect when using 1 word/burst
  DmaRegs.CH1.TRANSFER_SIZE = 127;		// Interrupt every frame (127 bursts/transfer)
  DmaRegs.CH1.SRC_TRANSFER_STEP = 1;	// Move to next word in buffer after each word in a burst
  DmaRegs.CH1.DST_TRANSFER_STEP = 0;	// Don't move destination address
  DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32) &sdata[0];			// Start address = buffer
  DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32) &sdata[0];		// Not needed unless using wrap function
  DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32) &McbspaRegs.DXR1.all;		// Start address = McBSPA DXR
  DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32) &McbspaRegs.DXR1.all;	// Not needed unless using wrap function
  DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1;	// Clear peripheral interrupt event flag
  DmaRegs.CH1.CONTROL.bit.SYNCCLR = 1;		// Clear sync flag
  DmaRegs.CH1.CONTROL.bit.ERRCLR = 1;	// Clear sync error flag
  DmaRegs.CH1.DST_WRAP_SIZE = 0xFFFF;		// Put to maximum - don't want destination wrap
  DmaRegs.CH1.SRC_WRAP_SIZE = 0xFFFF;		// Put to maximum - don't want source wrap
  DmaRegs.CH1.MODE.bit.SYNCE = 0;         		// No sync signal
  DmaRegs.CH1.MODE.bit.SYNCSEL = 0;       		// No sync signal
  DmaRegs.CH1.MODE.bit.CHINTE = 1;			// Enable channel interrupt
  DmaRegs.CH1.MODE.bit.CHINTMODE = 1;		// Interrupt at end of transfer
  DmaRegs.CH1.MODE.bit.PERINTE = 1;			// Enable peripheral interrupt event
  DmaRegs.CH1.MODE.bit.PERINTSEL = DMA_MXEVTA;		// Peripheral interrupt select = McBSP MXSYNCA
  DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1;  		// Clear any spurious interrupt flags

  // Channel 2, McBSPA Receive
  DmaRegs.CH2.MODE.bit.CHINTE = 0;
  DmaRegs.CH2.BURST_SIZE.all = 0;		// 1 word/burst
  DmaRegs.CH2.SRC_BURST_STEP = 0;		// no effect when using 1 word/burst
  DmaRegs.CH2.DST_BURST_STEP = 0;		// no effect when using 1 word/burst
  DmaRegs.CH2.TRANSFER_SIZE = 127;		// Interrupt every 127 bursts/transfer
  DmaRegs.CH2.SRC_TRANSFER_STEP = 0;	// Don't move source address
  DmaRegs.CH2.DST_TRANSFER_STEP = 1;	// Move to next word in buffer after each word in a burst
  DmaRegs.CH2.SRC_ADDR_SHADOW = (Uint32) &McbspaRegs.DRR1.all;			// Start address = McBSPA DRR
  DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = (Uint32) &McbspaRegs.DRR1.all;		// Not needed unless using wrap function
  DmaRegs.CH2.DST_ADDR_SHADOW = (Uint32) &rdata[0];		// Start address = Receive buffer (for McBSP-A)
  DmaRegs.CH2.DST_BEG_ADDR_SHADOW = (Uint32) &rdata[0];	// Not needed unless using wrap function
  DmaRegs.CH2.CONTROL.bit.PERINTCLR = 1;	// Clear peripheral interrupt event flag
  DmaRegs.CH2.CONTROL.bit.SYNCCLR = 1;		// Clear sync flag
  DmaRegs.CH2.CONTROL.bit.ERRCLR = 1;	// Clear sync error flag
  DmaRegs.CH2.DST_WRAP_SIZE = 0xFFFF;		// Put to maximum - don't want destination wrap
  DmaRegs.CH2.SRC_WRAP_SIZE = 0xFFFF;		// Put to maximum - don't want source wrap
  DmaRegs.CH2.MODE.bit.CHINTE = 1;			// Enable channel interrupt
  DmaRegs.CH2.MODE.bit.CHINTMODE = 1;		// Interrupt at end of transfer
  DmaRegs.CH2.MODE.bit.PERINTE = 1;			// Enable peripheral interrupt event
  DmaRegs.CH2.MODE.bit.PERINTSEL = DMA_MREVTA;  // Peripheral interrupt select = McBSP MRSYNCA
  DmaRegs.CH2.CONTROL.bit.PERINTCLR = 1;  		// Clear any spurious interrupt flags
  EDIS;
}

// DMA Initialization for data size > 16-bit and <= 32-bit.

void init_dma_32()
{
  EALLOW;
  DmaRegs.DMACTRL.bit.HARDRESET = 1;
  asm(" NOP");						   // Only 1 NOP needed per Design

  // Channel 1, McBSPA transmit
  DmaRegs.CH1.BURST_SIZE.all = 1;		// 2 word/burst
  DmaRegs.CH1.SRC_BURST_STEP = 1;		// increment 1 16-bit addr. btwn words
  DmaRegs.CH1.DST_BURST_STEP = 1;		// increment 1 16-bit addr. btwn words
  DmaRegs.CH1.TRANSFER_SIZE = 63;		// Interrupt every 63 bursts/transfer
  DmaRegs.CH1.SRC_TRANSFER_STEP = 1;	// Move to next word in buffer after each word in a burst
  DmaRegs.CH1.DST_TRANSFER_STEP = 0xFFFF;	// Go back to DXR2
  DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32) &sdata[0];	// Start address = buffer
  DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32) &sdata[0];		    // Not needed unless using wrap function
  DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32) &McbspaRegs.DXR2.all;		// Start address = McBSPA DXR2
  DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32) &McbspaRegs.DXR2.all;	// Not needed unless using wrap function
  DmaRegs.CH1.CONTROL.bit.SYNCCLR = 1;		// Clear sync flag
  DmaRegs.CH1.CONTROL.bit.ERRCLR = 1;	// Clear sync error flag
  DmaRegs.CH1.DST_WRAP_SIZE = 0xFFFF;		// Put to maximum - don't want destination wrap
  DmaRegs.CH1.SRC_WRAP_SIZE = 0xFFFF;		// Put to maximum - don't want source wrap
  DmaRegs.CH1.MODE.bit.SYNCE = 0;         		// No sync signal
  DmaRegs.CH1.MODE.bit.SYNCSEL = 0;       		// No sync signal
  DmaRegs.CH1.MODE.bit.CHINTE = 1;			// Enable channel interrupt
  DmaRegs.CH1.MODE.bit.CHINTMODE = 1;		// Interrupt at end of transfer
  DmaRegs.CH1.MODE.bit.PERINTE = 1;			// Enable peripheral interrupt event
  DmaRegs.CH1.MODE.bit.PERINTSEL = DMA_MXEVTA;		// Peripheral interrupt select = McBSP MXSYNCA
  DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1;  		// Clear any spurious interrupt flags

  // Channel 2, McBSPA Receive
  DmaRegs.CH2.BURST_SIZE.all = 1;		// 2 words/burst
  DmaRegs.CH2.SRC_BURST_STEP = 1;		// Increment 1 16-bit addr. btwn words
  DmaRegs.CH2.DST_BURST_STEP = 1;	    // Increment 1 16-bit addr. btwn words
  DmaRegs.CH2.TRANSFER_SIZE = 63;		// Interrupt every 63 bursts/transfer
  DmaRegs.CH2.SRC_TRANSFER_STEP = 0xFFFF;	// Decrement  back to DRR2
  DmaRegs.CH2.DST_TRANSFER_STEP = 1;	// Move to next word in buffer after each word in a burst
  DmaRegs.CH2.SRC_ADDR_SHADOW = (Uint32) &McbspaRegs.DRR2.all;			// Start address = McBSPA DRR
  DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = (Uint32) &McbspaRegs.DRR2.all;		// Not needed unless using wrap function
  DmaRegs.CH2.DST_ADDR_SHADOW = (Uint32) &rdata[0];		// Start address = Receive buffer (for McBSP-A)
  DmaRegs.CH2.DST_BEG_ADDR_SHADOW = (Uint32) &rdata[0];	// Not needed unless using wrap function
  DmaRegs.CH2.CONTROL.bit.SYNCCLR = 1;		// Clear sync flag
  DmaRegs.CH2.CONTROL.bit.ERRCLR = 1;	// Clear sync error flag
  DmaRegs.CH2.DST_WRAP_SIZE = 0xFFFF;		// Put to maximum - don't want destination wrap
  DmaRegs.CH2.SRC_WRAP_SIZE = 0xFFFF;		// Put to maximum - don't want source wrap
  DmaRegs.CH2.MODE.bit.CHINTE = 1;			// Enable channel interrupt
  DmaRegs.CH2.MODE.bit.CHINTMODE = 1;		// Interrupt at end of transfer
  DmaRegs.CH2.MODE.bit.PERINTE = 1;			// Enable peripheral interrupt event
  DmaRegs.CH2.MODE.bit.PERINTSEL = DMA_MREVTA;	// Peripheral interrupt select = McBSP MRSYNCA
  DmaRegs.CH2.CONTROL.bit.PERINTCLR = 1;  		// Clear any spurious interrupt flags
  EDIS;
}
void start_dma (void)
{
  EALLOW;
  DmaRegs.CH1.CONTROL.bit.RUN = 1;	         // Start DMA Transmit from McBSP-A
  DmaRegs.CH2.CONTROL.bit.RUN = 1;           // Start DMA Receive from McBSP-A

  EDIS;
}
// INT7.1
interrupt void local_D_INTCH1_ISR(void)		// DMA Ch1
{
   	EALLOW;									// NEED TO EXECUTE EALLOW INSIDE ISR !!!
	DmaRegs.CH1.CONTROL.bit.RUN=0;		    // Re-enable DMA CH1. Should be done every transfer
   	PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; // To receive more interrupts from this PIE group, acknowledge this interrupt

    EDIS;
	return;
}

// INT7.2
interrupt void local_D_INTCH2_ISR(void)		// DMA Ch2
{
    Uint16 i;
    EALLOW;									// NEED TO EXECUTE EALLOW INSIDE ISR !!!
	DmaRegs.CH2.CONTROL.bit.RUN = 0;		// Re-enable DMA CH2. Should be done every transfer
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; // To receive more interrupts from this PIE group, acknowledge this interrupt
    for (i=0; i<128; i++)
		{
		if(WORD_SIZE == 8)
        {
          if( (rdata[i]&0x00FF) !=(sdata[i]&0x00FF)) error( ); // Check for correct received data
        }
        else if (WORD_SIZE == 16)
		{
		  if (rdata[i] != sdata[i])  error();  // STOP if there is an error !!
        }
		else if (WORD_SIZE == 32)
		{
		  if ((rdata[i])!=(sdata[i])) error ();
		}
   }
	 EDIS;
	 return;

}

//===========================================================================
// No more.
//===========================================================================