📄 xsmsl.h
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/******************************************************************************
**
** COPYRIGHT (C) 2000, 2001 Intel Corporation.
**
** This software as well as the software described in it is furnished under
** license and may only be used or copied in accordance with the terms of the
** license. The information in this file is furnished for informational use
** only, is subject to change without notice, and should not be construed as
** a commitment by Intel Corporation. Intel Corporation assumes no
** responsibility or liability for any errors or inaccuracies that may appear
** in this document or any software that may be provided in association with
** this document.
** Except as permitted by such license, no part of this document may be
** reproduced, stored in a retrieval system, or transmitted in any form or by
** any means without the express written consent of Intel Corporation.
**
** FILENAME: XsMsl.h
**
** PURPOSE: This header file contains all the MSL baseband device
** registers.
**
** LAST MODIFIED: June 13, 2002
******************************************************************************/
#ifndef _XsMsl_h_
#define _XsMsl_h_
/*
*******************************************************************************
* MSL Base Device Register Address.
*******************************************************************************
*/
#define XSMSL_REGISTER_BASE 0x41400000 // Register Address Base
#define XSMSL_CHANNEL_NUM 7 // Number of Channels in MSL
#define FIFO_LEN 64U // I/O Fifo length in bytes
/*
*******************************************************************************
* MSL Channel Configuration.Register
*******************************************************************************
*/
#define TXBLOCK_SHIFT 8
#define TXBLOCK_4B (0U << TXBLOCK_SHIFT) // Transmit block size - 4 Bytes
#define TXBLOCK_8B (1U << TXBLOCK_SHIFT) // Transmit block size - 8 Bytes
#define TXBLOCK_16B (2U << TXBLOCK_SHIFT) // Transmit block size - 16 Bytes
#define TXBLOCK_32B (3U << TXBLOCK_SHIFT) // Transmit block size - 32 Bytes
#define RXSERVICE_SHIFT 21
#define RXSERVICE_NONE (0U << RXSERVICE_SHIFT) // Receive FIFO service select - None
#define RXSERVICE_DMA (1U << RXSERVICE_SHIFT) // Receive FIFO service select - DMA
#define RXSERVICE_INT (2U << RXSERVICE_SHIFT) // Receive FIFO service select - INT
#define TXSERVICE_SHIFT 5
#define TXSERVICE_NONE (0U << TXSERVICE_SHIFT) // Transmit FIFO service select - None
#define TXSERVICE_DMA (1U << TXSERVICE_SHIFT) // Transmit FIFO service select - DMA
#define TXSERVICE_INT (2U << TXSERVICE_SHIFT) // Transmit FIFO service select - INT
#define RXTHRESHLEVEL_SHIFT 19
#define RXTHRESHLEVEL_4B (0U << RXTHRESHLEVEL_SHIFT) // Receive FIFO threshlevel - 4 bytes
#define RXTHRESHLEVEL_8B (1U << RXTHRESHLEVEL_SHIFT) // Receive FIFO threshlevel - 8 bytes
#define RXTHRESHLEVEL_16B (2U << RXTHRESHLEVEL_SHIFT) // Receive FIFO threshlevel - 16 bytes
#define RXTHRESHLEVEL_32B (3U << RXTHRESHLEVEL_SHIFT) // Receive FIFO threshlevel - 32 bytes
#define TXTHRESHLEVEL_SHIFT 3
#define TXTHRESHLEVEL_4B (0U << TXTHRESHLEVEL_SHIFT) // Transmit FIFO threshlevel - 4 bytes
#define TXTHRESHLEVEL_8B (1U << TXTHRESHLEVEL_SHIFT) // Transmit FIFO threshlevel - 8 bytes
#define TXTHRESHLEVEL_16B (2U << TXTHRESHLEVEL_SHIFT) // Transmit FIFO threshlevel - 16 bytes
#define TXTHRESHLEVEL_32B (3U << TXTHRESHLEVEL_SHIFT) // Transmit FIFO threshlevel - 32 bytes
#define EOCSERVICE (1U << 24) // End of (Descriptor) Chain Service
#define RXWAITENABLE_SHIFT 18
#define RXDFCENABLE (1U << RXWAITENABLE_SHIFT) // Receive Direct Flow Control enable
#define RXMFCENABLE (1U << 17) // Receive Message Flow Control enable
#define RXENABLE_SHIFT 16
#define RXENABLE (1U << RXENABLE_SHIFT) // Receive FIFO channel enable
#define TXWAITENABLE_SHIFT 2
#define TXDFCENABLE (1U << TXWAITENABLE_SHIFT) // Transmit Direct Flow Control enable
#define TXMFCENABLE (1U << 1) // Transmit Message Flow Control enable
#define TXENABLE_SHIFT 0
#define TXENABLE (1U << TXENABLE_SHIFT) // Transmit FIFO channel enable
/*
*******************************************************************************
* MSL Channel Status Register.(Read Only)
*******************************************************************************
*/
#define RXEOM_3 (1U << 31) // 4th byte EOM
#define RXEOM_2 (1U << 30) // 3rd byte EOM
#define RXEOM_1 (1U << 29) // 2nd byte EOM
#define RXEOM_0 (1U << 28) // 1st byte EOM
#define RXEOM_MASK (0xFU << 28) // EOM mask
#define RXEOM_FIFO (1U << 25) // Channel Fifo has Received EOM
#define RXWAIT (1U << 24) // Receive Channel in Wait State
#define RXEMPTY (1U << 23) // Receive FIFO Empty
#define RXFULL (1U << 22) // Receive FIFO Full
#define RXFULLNESS_SHIFT (16U) // Bit Position of RX Fullness
#define RXFULLNESS_MASK (0x3FU << 16) // Fullness of Receive FIFO
#define TXWAIT (1U << 8) // Transmit Channel in Wait State
#define TXEMPTY (1U << 7) // Transmit FIFO Empty
#define TXFULL (1U << 6) // Transmit FIFO Full
#define TXFULLNESS_MASK (0x3FU << 0) // Fullness of Transmit FIFO
#define TXFULLNESS_SHIFT (0U) // Bit Position of TX Fullness
/*
*******************************************************************************
* MSL Interrupt ID Register
*******************************************************************************
*/
#define TX_INT7 (1U << 23) // Transmit FIFO Interrupt Channel 7
#define TX_INT6 (1U << 22) // Transmit FIFO Interrupt Channel 6
#define TX_INT5 (1U << 21) // Transmit FIFO Interrupt Channel 5
#define TX_INT4 (1U << 20) // Transmit FIFO Interrupt Channel 4
#define TX_INT3 (1U << 19) // Transmit FIFO Interrupt Channel 3
#define TX_INT2 (1U << 18) // Transmit FIFO Interrupt Channel 2
#define TX_INT1 (1U << 17) // Transmit FIFO Interrupt Channel 1
#define EOC_INT7 (1U << 15) // End of (Descriptor) Chain Interrupt Channel 7
#define EOC_INT6 (1U << 14) // End of (Descriptor) Chain Interrupt Channel 6
#define EOC_INT5 (1U << 13) // End of (Descriptor) Chain Interrupt Channel 5
#define EOC_INT4 (1U << 12) // End of (Descriptor) Chain Interrupt Channel 4
#define EOC_INT3 (1U << 11) // End of (Descriptor) Chain Interrupt Channel 3
#define EOC_INT2 (1U << 10) // End of (Descriptor) Chain Interrupt Channel 2
#define EOC_INT1 (1U << 9) // End of (Descriptor) Chain Interrupt Channel 1
#define RX_INT7 (1U << 7) // Receive FIFO Interrupt Channel 7
#define RX_INT6 (1U << 6) // Receive FIFO Interrupt Channel 6
#define RX_INT5 (1U << 5) // Receive FIFO Interrupt Channel 5
#define RX_INT4 (1U << 4) // Receive FIFO Interrupt Channel 4
#define RX_INT3 (1U << 3) // Receive FIFO Interrupt Channel 3
#define RX_INT2 (1U << 2) // Receive FIFO Interrupt Channel 2
#define RX_INT1 (1U << 1) // Receive FIFO Interrupt Channel 1
// Above list of Interrupts Unused for now
#define CHANNEL_BITS (0x7FU ) // 1 bit for every channel (mask)
#define RXFIFO_OFFSET 1U // Rx FIFO interrupt bit offset
#define TXFIFO_OFFSET 17U // Tx FIFO interrupt bit offset
#define EOC_OFFSET 9 // EOC Service interrupt bit offset
//#define VGPIO_INT (1U << 0) // GPIO interrupt
/*
*******************************************************************************
* MSL Frequency Register
*******************************************************************************
*/
#define BBFREQ_SHIFT 4U // Clock Frequency Divider Offset
#define BBFREQ_MAX 0xFF // Maximum Divisor for BBFREQ
/*
*******************************************************************************
* MSL Interface Width Register
*******************************************************************************
*/
#define RX_ITFC_SHIFT 16
#define RX_ITFC_1BIT (0U << RX_ITFC_SHIFT) // 1 bit Receive Interface Width
#define RX_ITFC_2BIT (1U << RX_ITFC_SHIFT) // 2 bit Receive Interface Width
#define RX_ITFC_4BIT (2U << RX_ITFC_SHIFT) // 4 bit Receive Interface Width
#define TX_ITFC_1BIT (0U << 0) // 1 bit Transmit Interface Width
#define TX_ITFC_2BIT (1U << 0) // 2 bit Transmit Interface Width
#define TX_ITFC_4BIT (2U << 0) // 4 bit Transmit Interface Width
/*
*******************************************************************************
* MSL VGPIO Channel Masks
*******************************************************************************
*/
#define VGPIO_CH0 (0x1U << 0) // channel 0 interrupt
#define VGPIO_CH1 (0x1U << 1) // channel 1 interrupt
#define VGPIO_CH2 (0x1U << 2) // channel 2 interrupt
#define VGPIO_CH3 (0x1U << 3) // channel 3 interrupt
#define VGPIO_CH4 (0x1U << 4) // channel 4 interrupt
#define VGPIO_CH5 (0x1U << 5) // channel 5 interrupt
#define VGPIO_CH6 (0x1U << 6) // channel 6 interrupt
#define VGPIO_CH7 (0x1U << 7) // channel 7 interrupt
#define VGPIO_CH8 (0x1U << 8) // channel 8 interrupt
#define VGPIO_CH9 (0x1U << 9) // channel 9 interrupt
#define VGPIO_CH10 (0x1U << 10) // channel 10 interrupt
#define VGPIO_CH11 (0x1U << 11) // channel 11 interrupt
#define VGPIO_CH12 (0x1U << 12) // channel 12 interrupt
#define VGPIO_CH13 (0x1U << 13) // channel 13 interrupt
#define VGPIO_CH14 (0x1U << 14) // channel 14 interrupt
#define VGPIO_CH15 (0x1U << 15) // channel 15 interrupt
#define VGPIO_CH16 (0x1U << 16) // channel 16 interrupt
#define VGPIO_CH17 (0x1U << 17) // channel 17 interrupt
#define VGPIO_CH18 (0x1U << 18) // channel 18 interrupt
#define VGPIO_CH19 (0x1U << 19) // channel 19 interrupt
#define VGPIO_CH20 (0x1U << 20) // channel 20 interrupt
#define VGPIO_CH21 (0x1U << 21) // channel 21 interrupt
#define VGPIO_CH22 (0x1U << 22) // channel 22 interrupt
#define VGPIO_CH23 (0x1U << 23) // channel 23 interrupt
#define VGPIO_CH24 (0x1U << 24) // channel 24 interrupt
#define VGPIO_CH25 (0x1U << 25) // channel 25 interrupt
#define VGPIO_CH26 (0x1U << 26) // channel 26 interrupt
#define VGPIO_CH27 (0x1U << 27) // channel 27 interrupt
#define VGPIO_CH28 (0x1U << 28) // channel 28 interrupt
#define VGPIO_CH29 (0x1U << 29) // channel 29 interrupt
#define VGPIO_CH30 (0x1U << 30) // channel 30 interrupt
#define VGPIO_CH31 (0x1U << 31) // channel 31 interrupt
/*
*******************************************************************************
* MSL Baseband Control Registers.
*******************************************************************************
*/
typedef struct XsMslRegsS {
UINT RESERVED0; //0x4140 0000 // Reserved Address Space
VUINT32 BBFIFO[XSMSL_CHANNEL_NUM]; // Receive/Transmit FIFO Registers
UINT RESERVED1[9]; // Reserved Address Space
VUINT32 BBCFG[XSMSL_CHANNEL_NUM]; // Configuration Registers
UINT RESERVED2[9]; // Reserved Address Space
VUINT32 BBSTAT[XSMSL_CHANNEL_NUM]; // Status Registers
UINT RESERVED3[9]; // Reserved Address Space
VUINT32 BBEOM[XSMSL_CHANNEL_NUM]; // EOM Registers
UINT RESERVED4[8]; // Reserved Address Space
// VUINT32 BBCSTP; // Channel Stop Threshold Register
// VUINT32 BBCSTR; // Channel Start Threshold Register
UINT RESERVED5[2]; // Reserved Address Space
VUINT32 BBIID; // Interrupt ID Register
UINT RESERVED6; // Reserved Address Space
VUINT32 BBFREQ; // Transmit Frequency Select Register
VUINT32 BBWAIT; // Wait Count Register
VUINT32 BBCST; // Clock Stop Time Register
// VUINT32 BBVGIL; // VGPIO Input Pin-Level Register
// VUINT32 BBVGOL; // VGPIO Output Pin-Level Register
// VUINT32 BBVGSR; // VGPIO Pin-Set Register
// VUINT32 BBVGCR; // VGPIO Pin Clear Register
// VUINT32 BBVGRE; // VGPIO Rising Edge Detect Register
// VUINT32 BBVGFE; // VGPIO Falling Edge Detect Register
// VUINT32 BBVGED; // VGPIO Edge-Detect Status Register
// VUINT32 BBVGVI; // VGPIO Value Interrupt Register
UINT RESERVED7[8]; // Reserved Address Space
UINT RESERVED8; // Reserved Address Space
VUINT32 BBWAKE; // Wake-Up Register
VUINT32 BBITFC; // Interface Width Register
} XsMslRegsT;
/*
*******************************************************************************
* DRIVER DEFINITIONS
*******************************************************************************
*/
#define MAX_BUFFER_SIZE 2048 // Buffersize to allocate for Receive Buffers
#define RX_SERVICE_MSK (0x7U << 21)
//#define nRX_SERVICE_MSK 0xFF1FFFFF // ~(7U << 21), save all settings but clear RX_SERVICE
#define TX_SERVICE_MSK (0x7U << 5)
//#define nTX_SERVICE_MSK 0xFFFFFF1F // ~(7U << 5), save all settings but clear TX_SERVICE
#define RX_MSK 0x03FF0000 // Save existing Rx Settings
#define TX_MSK 0x000007FF // Save existing Tx Settings
#define BBCFG_RESERVED_MSK 0x03FF07FF // Save Tx/Rx Settings
#define MSL_TIMEOUT_S 5U // Timeout in number of seconds
#endif // _XsMsl_h_⌨️ 快捷键说明
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