xsmslapi.h

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/******************************************************************************
**
**  COPYRIGHT (C) 2000, 2001 Intel Corporation.
**
**  This software as well as the software described in it is furnished under 
**  license and may only be used or copied in accordance with the terms of the 
**  license. The information in this file is furnished for informational use 
**  only, is subject to change without notice, and should not be construed as 
**  a commitment by Intel Corporation. Intel Corporation assumes no 
**  responsibility or liability for any errors or inaccuracies that may appear 
**  in this document or any software that may be provided in association with 
**  this document. 
**  Except as permitted by such license, no part of this document may be 
**  reproduced, stored in a retrieval system, or transmitted in any form or by 
**  any means without the express written consent of Intel Corporation. 
**
**  FILENAME:       XsMslApi.h
**
**  PURPOSE:        <Module description here>
**
**  LAST MODIFIED:  $Modtime: 7/17/03 1:01p $
******************************************************************************/
#ifndef _XsMslApi_h_
#define _XsMslApi_h_

#include "XsMsl.h"

/*
*******************************************************************************
*    MSL Configuration Structure
*******************************************************************************
*/
typedef struct MslCfgS {
    UINT    channel;            // Channel number (1-7, 0 = ALL)
    UINT    tx_wait;            // Number of cycles before retransmit (1-1023)
    UINT    clock_count;        // Number of extra clock cycles (0-14, 15 - never stops)
    UINT    freq_divider;       // The frequency divider
    UINT    bit_width;          // Bit width 1, 2 or 4
    UINT    rx_length;          // Size of the receive buffer.
    UINT    tx_length;          // Size of the transmit buffer.
    UINT    tx_blocksize;       // Size of the transmit block
    UINT    rx_fifo_service;    // Receive FIFO service
    UINT    tx_fifo_service;    // Transmit FIFO service
    UINT    rx_threshold;       // Receive threshold
    UINT    tx_threshold;       // Transmit threshold
    UINT    rx_flowcontrol;     // Receive flow control
    UINT    tx_flowcontrol;     // Transmit flow control
} MslCfgT;

/*
*******************************************************************************
*    MSL DMA Status Structure
*******************************************************************************
*/
typedef struct MslDmaStatusS {
	INT busErrorIntCount;
	INT endIntCount;
	INT startIntCount;
	INT	stopIntCount;
} MslDmaStatusT;

/*
*******************************************************************************
*    MSL Enumerations.
*******************************************************************************
*/

typedef enum XsMslTxBlockSizeE
{
    BLOCKSIZE_4B  = 4,
    BLOCKSIZE_8B  = 8,
    BLOCKSIZE_16B = 16,
    BLOCKSIZE_32B = 32
} XsMslTxBlockSizeT;
    
typedef enum XsMslInterfaceWidthE
{
    IF_1BIT  = 1,
    IF_2BITS = 2,
    IF_4BITS = 4
} XsMslInterfaceWidthT;

typedef enum XsMslFifoServiceE
{
    FIFO_SERVICE_POLL = 0,
    FIFO_SERVICE_INT,
    FIFO_SERVICE_DMA
} XsMslFifoServiceT;

typedef enum XsMslRxFlowControlE
{
    NONE = 0,
    DFC,
    MFC
} XsMslFlowControlT;

typedef enum XsMslThresholdE
{
    THRESHOLD_4B = 4,
    THRESHOLD_8B = 8,
    THRESHOLD_16B = 16,
    THRESHOLD_32B = 32
} XsMslThresholdT;

typedef enum XsMslIntrMskE
{
    RXFIFO_MSK     = CHANNEL_BITS << RXFIFO_OFFSET,  
    TXFIFO_MSK     = CHANNEL_BITS << TXFIFO_OFFSET,
    EOCSERVICE_MSK = CHANNEL_BITS << EOC_OFFSET
//    VGPIO_MSK      = VGPIO_INT
} XsMslIntrMskT;

typedef enum XsMslConfigChannelE
{
    MSLTXCHAN = 1,
    MSLRXCHAN,
    MSLTXRXCHAN
} XsMslConfigChannelT;

/*
*******************************************************************************
*    MSL Definitions
*******************************************************************************
*/
#define DEFAULT_CHANNEL     0        // Channel number 1-7, 0 = ALL
#define DEFAULT_TX_WAIT     100      // Number of cycles before retransmit (1-1023)
#define DEFAULT_CLOCK_COUNT 0        // Extra clock cycles (0-14, 15 - never stops)
#define DEFAULT_FREQ_DIV    255      // The frequency divider (196KHZ)
#define RX_DEFAULT_LENGTH   64       // Size of the receive packet
#define TX_DEFAULT_LENGTH   64       // Size of the transmit packet
#define MSL_RX_NUM_DEV_DESC 1        // Number of receive device DMA descriptors
#define MSL_RX_NUM_MEM_DESC 1        // Number of receive memory DMA descriptors
#define MSL_TX_NUM_DEV_DESC 1        // Number of transmit device DMA descriptors
#define MSL_TX_NUM_MEM_DESC 1        // Number of transmit memory DMA descriptors

/*
*******************************************************************************
*    MSL Baseband Error Codes.
*******************************************************************************
*/

#define ERR_S_MSL_NONE                0x00
#define ERR_S_MSL_TRANSMIT            0x01
#define ERR_S_MSL_TRANSMIT_INT        0x02
#define ERR_S_MSL_TRANSMIT_DMA        0x03
#define ERR_S_MSL_RECEIVE             0x04
#define ERR_S_MSL_RECEIVE_INT		  0x05
#define ERR_S_MSL_RECEIVE_DMA         0x06
#define ERR_S_MSL_TX_CONFIG      	  0x07
#define ERR_S_MSL_RX_CONFIG      	  0x08
#define ERR_S_MSL_SETUP               0x09
#define ERR_S_MSL_SHUTDOWN            0x0A
#define ERR_S_MSL_INT_HANDLE          0x0B
#define ERR_S_MSL_INVALID_CHANNEL     0x0C
#define ERR_S_MSL_DMAINT_TX_ENABLE    0x0D
#define ERR_S_MSL_DMAINT_TX_DISABLE   0x0E
#define ERR_S_MSL_DMAINT_RX_ENABLE    0x0F
#define ERR_S_MSL_DMAINT_RX_DISABLE   0x10

#define ERR_S2_MSL_NONE               0x00    // No Extra information is necessary
#define ERR_S2_MSL_DMAINT             0x01
#define ERR_S2_MSL_DMA_CONFIG         0x02
#define ERR_S2_MSL_INVALID_CHANNEL    0x03

/*
*******************************************************************************
*    MSL Baseband Function Pointers.
*******************************************************************************
*/
typedef UINT32  (*XsMslHWSetupT) (PVOID ctxP);
typedef VOID    (*XsMslHWShutdownT) (PVOID ctxP);
typedef UINT32  (*XsMslTransmitPacketT) (PVOID ctxP, UINT32 channel_offset, PCHAR bufferP, UINT32 length);
typedef UINT32  (*XsMslReceivePacketT) (PVOID ctxP, UINT32 channel_offset, PCHAR bufferP, UINT32 length);
typedef UINT32  (*XsMslChannelStatusT) (PVOID ctxP, UINT32 channel_offset);
typedef UINT32  (*XsMslPacketAvailT) (PVOID ctxP, UINT32 channel_offset);
typedef UINT32  (*XsMslChangeConfigurationT) (PVOID ctxP, UINT32 channel_offset);
typedef UINT32  (*XsMslEnableTxServiceT) (PVOID ctxP, UINT32 channel_offset);
typedef UINT32  (*XsMslEnableRxServiceT) (PVOID ctxP, UINT32 channel_offset);
typedef UINT32  (*XsMslDisableTxServiceT) (PVOID ctxP, UINT32 channel_offset);
typedef UINT32  (*XsMslDisableRxServiceT) (PVOID ctxP, UINT32 channel_offset);
typedef VOID    (*RegDumpT) (PVOID ctxP);

#endif // _XsMslApi_h_