xslcdcontroller.h

优龙YLP270开发板 光盘自带的BIOS和实验例程源码 强烈推荐

/*************************************************************************
**
**  COPYRIGHT (C) 2000, 2001 Intel Corporation.
**
**  This software as well as the software described in it is furnished under 
**  license and may only be used or copied in accordance with the terms of the 
**  license. The information in this file is furnished for informational use 
**  only, is subject to change without notice, and should not be construed as 
**  a commitment by Intel Corporation. Intel Corporation assumes no 
**  responsibility or liability for any errors or inaccuracies that may appear 
**  in this document or any software that may be provided in association with 
**  this document. 
**  Except as permitted by such license, no part of this document may be 
**  reproduced, stored in a retrieval system, or transmitted in any form or by 
**  any means without the express written consent of Intel Corporation. 
**
**  FILENAME:  		lcdcontroller.h
**
**  PURPOSE:   		%qEnter module description:$
**
**  LAST MODIFIED: 	sle - 01/11/01
**  EAS VERSION:    2.1
******************************************************************************/

#ifndef _xslcdcontroller_h
#define _xslcdcontroller_h

#ifdef LCD_GLOBALS
#define EXTRN
#else
#define EXTRN extern
#endif

#define LCDCTRL_REG_BASE ((volatile LCDCtrlRegsT *)0x44000000)

// Lcd Controller's Registers definition

struct lccr0Bits {
	unsigned  enb			:1;
	unsigned  cms			:1;
	unsigned  sds			:1;
	unsigned  ldm			:1;
	unsigned  sfm			:1;
	unsigned  ium			:1;
	unsigned  efm			:1;
	unsigned  pas			:1;
	unsigned  ble			:1;
	unsigned  dpd			:1;
	unsigned  dis			:1;
	unsigned  qdm			:1;
	unsigned  pdd			:8;
	unsigned  bm			:1;
	unsigned  oum			:1;
	unsigned  ldt			:1;
	unsigned  rsm			:1;
	unsigned  rtm			:1;
	unsigned  rsvd2			:7;
};

struct lccr1Bits {
	unsigned  ppl			:10;
	unsigned  hsw			:6;
	unsigned  elw			:8;
	unsigned  blw			:8;
};

struct lccr2Bits {
	unsigned  lpp			:10;
	unsigned  vsw			:6;
	unsigned  efw			:8;
	unsigned  bfw			:8;
};

struct lccr3Bits {
	unsigned  pcd			:8;
	unsigned  acb			:8;
	unsigned  api			:4;
	unsigned  vsp			:1;
	unsigned  hsp			:1;
	unsigned  pcp			:1;
	unsigned  oep			:1;
	unsigned  bpp			:3;
	unsigned  dpc			:1;
	unsigned  rsvd0			:4;
};

struct lcsrBits {
	unsigned  lfd			:1;
	unsigned  bau			:1;
	unsigned  ber			:1;
	unsigned  abc			:1;
	unsigned  iol			:1;
	unsigned  iul			:1;
	unsigned  iou			:1;
	unsigned  iuu			:1;
	unsigned  ool			:1;
	unsigned  oul			:1;
	unsigned  oou			:1;
	unsigned  ouu			:1;
	unsigned  rsvd0			:20;
};

typedef struct lcdregs {
  struct lccr0Bits			lccr0;
  struct lccr1Bits			lccr1;
  struct lccr2Bits			lccr2;
  struct lccr3Bits			lccr3;
  VUINT32 reserved1[4] ;   // 0x44000010 thru 0x4400001F
  VUINT32 FBR0 ;  // DMA Channel 0 Frame Branch Register  - 0x4400 0020
  VUINT32 FBR1 ;  // DMA Channel 1 Frame Branch Register  - 0x4400 0024
  VUINT32 reserved2[4] ;   // 0x44000028 thru 0x44000037
  struct lcsrBits			lcsr; 
  VUINT32 LIIDR ; // LCD Controller InterruptID Register  - 0x4400 003C
  VUINT32 TRGBR ; // TMED RGB Seed Register               - 0x4400 0040
  VUINT32 TCR ;   // TMED Control Register                - 0x4400 0044
  VUINT32 reserved3[110] ; // 0x44000048 thru 0x440001FF
  VUINT32 FDADR0 ;// DMA Channel 0 Frame Descriptor Address Register - 0x4400 0200
  VUINT32 FSADR0 ;// DMA Channel 0 Frame Source Address Register     - 0x4400 0204
  VUINT32 FIDR0 ; // DMA Channel 0 Frame ID Register       - 0x4400 0208
  VUINT32 LDCMD0 ;// DMA Channel 0 Command Register        - 0x4400 020C
  VUINT32 FDADR1 ;// DMA Channel 1 Frame Descriptor Address Register - 0x4400 0210
  VUINT32 FSADR1 ;// DMA Channel 1 Frame Source Address Register     - 0x4400 0214
  VUINT32 FIDR1 ; // DMA Channel 1 Frame ID Register       - 0x4400 0218
  VUINT32 LDCMD1 ;// DMA Channel 1 Command Register        - 0x4400 021C
} LcdRegT;

typedef struct LCDFrameDescriptorS {
	UINT32 FDADR;
	UINT32 FSADR;
	UINT32 FIDR;
	UINT32 LDCMD;
} LCDFrameDescriptorT;

typedef enum Panel_PanelType_E {
  Panel_TypeLcd = 1,
  Panel_TypeEncoder = 2
} Panel_PanelType_T;

/* Panel geometry for LCD setup
 */
typedef struct DM_LcdDefinition_S {
  int panelWidth;
  int panelHeight;
  int extraLines;

  char panelType;
  char dualPanel;
  char activeDisplay;
  char colorDepth;

  char horizSyncPW;
  char horizELW;
  char horizBLW;
  //char reserved1;

  char vertSyncPW;
  char vertEFW;
  char vertBFW;
  //char reserved2;

  int  pixelClkDiv;
  char frameSyncPol;
  char horizSyncPol;
  char clockPol;
  char outputEnaPol;

  short acBiasCount;
  //short reserved3;
} DM_LcdDefinition_T;

/* Frame header contains a pointer to the memory region which holds the
 * palette and the pixel data. The palette and pixel data are dependent on
 * the current colorspace and geometry. Keep this structure a multiple of
 * 16 in size.
 */

typedef struct FrameHeaderS {
    int size;                 // Total size of the frame in bytes.
    int horizPixel;
    int vertPixel;
    int extraLines;
    LCDFrameDescriptorT DmaDescriptor;
} FrameHeaderT;

typedef struct FrameS
{
    FrameHeaderT header;
    UINT16 buffer[1];
} FrameT;

extern FrameT *frameP;
extern UINT16 XsLcdBg;       // Background color for character output.
extern UINT16 XsLcdFg;       // Foreground color for character output.
extern UINT8 XsLcdFontScale; // Scaling factor for the font.
extern int XsLcdTask;

/*----------------------------------------------------------------------
 * Statistics
 */
typedef struct LCD_Stats_S {
  int frameCount;

  int iolError;
  int iulError;
  int iouError;
  int iuuError;

  int oolError;
  int oulError;
  int oouError;
  int ouuError;

  int busError;
  int noClear;
} LCD_Stats_T;

/*----------------------------------------------------------------------
 * Pixel clock rates
 */
 
typedef struct LCD_PixelClock_S {
  int clockSpeed;
  int fast;
  int slow;
  int lcd;
} LCD_PixelClock_T;

typedef struct  LcdContextS* LcdContextPT; // Need for dumb single-pass compiler.

/* BEGIN LCD Control Register 0 (LCCR0) definitions */
#define LCD_LCCR0_ENB_LCDEN ( 0x1 << 0 ) /* LCD controller enabled */
#define LCD_LCCR0_CMS_MONO  ( 0x1 << 1 ) /* Monochrome operation */
#define LCD_LCCR0_SDS_DUAL  ( 0x1 << 2 ) /* Dual-panel display enabled */
#define LCD_LCCR0_LDM_NOINT ( 0x1 << 3 ) /* LCD disable done condition does not
                                            generate an interrupt */
#define LCD_LCCR0_SFM_SOFNOINT ( 0x1 << 4 ) /* SOF condition does not
                                               generate an interrupt */
#define LCD_LCCR0_IUM_FIFONOINT ( 0x1 << 5 ) /* Input FIFO underrun errors do
                                                not generate an interrupt*/
#define LCD_LCCR0_EFM_EOFNOINT ( 0x1 << 6 ) /* End of Frame (EOF) does not
                                               generate an interrupt */
#define LCD_LCCR0_PAS_ACTDISP  ( 0x1 << 7 ) /* Active or TFT display op enabled */
#define LCD_LCCR0_BLE_BIGENDN  ( 0x1 << 8 ) /* Big Endian operation enabled */
#define LCD_LCCR0_DPD_DBLPIX   ( 0x1 << 9 ) /* Double pixel operation enabled */
#define LCD_LCCR0_DIS         ( 0x1 << 10 ) /* LCD Controller has been disabled */
#define LCD_LCCR0_QDM_NOINT   ( 0x1 << 11 ) /* QD status does not generate int */
#define LCD_LCCR0_LCDT   ( 0x1 << 22 )
#define LCD_LCCR0_RDSTM   ( 0x1 << 23 )