xspwm.h

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/******************************************************************************
**
**  COPYRIGHT (C) 2000, 2001 Intel Corporation.
**
**  This software as well as the software described in it is furnished under 
**  license and may only be used or copied in accordance with the terms of the 
**  license. The information in this file is furnished for informational use 
**  only, is subject to change without notice, and should not be construed as 
**  a commitment by Intel Corporation. Intel Corporation assumes no 
**  responsibility or liability for any errors or inaccuracies that may appear 
**  in this document or any software that may be provided in association with 
**  this document. 
**  Except as permitted by such license, no part of this document may be 
**  reproduced, stored in a retrieval system, or transmitted in any form or by 
**  any means without the express written consent of Intel Corporation. 
**
**  FILENAME:  		XsPwm.h
**
**  PURPOSE:   		This is the main header file for Pulse Width Modulation.
**
**  LAST MODIFIED: 	$Modtime: 7/17/03 1:01p $
**  EAS VERSION:    2.1
******************************************************************************/

#ifndef _XSPWM_H
#define _XSPWM_H

/* PWM Control Registers (CTRL) definitions */
#define PWM_CTRL_MASK           0x7F
#define PWM_CTRL_PRESCALE_SHIFT 0
#define PWM_CTRL_PRESCALE_MASK  0x3F     /* Mask for accessing PRESCALE */
#define PWM_CTRL_PWM_SD     ( 0x1 << 6 ) /* Abrupt shutdown of PWM when
                                            processor transitions to
                                            Unit Stop Clk or Suspend */
// bit 8-31 reserved

/* PWM Duty Cycle Registers (DUTY) definitions */
#define PWM_DUTY_MASK           0x7FF
#define PWM_DUTY_DCYCLE_SHIFT   0
#define PWM_DUTY_DCYCLE_MASK    0x3FF         /* Mask for accessing DCYCLE */
#define PWM_DUTY_FDCYCLE        ( 0x1 << 10 ) /* PWM output is full duty
                                                 cycle. The DCYCLE setting
                                                 is ignored*/
// bits 11-31 reserved

/* PWM Period Registers (PERVAL) definitions */
#define PWM_PERVAL_SHIFT    0
#define PWM_PERVAL_MASK     0x3FF
// bits 10-31 reserved

/* Address of Cotulla Pulse Width Modulation registers */
#define PWM0_REG_BASE 0x40B00000
#define PWM1_REG_BASE 0x40C00000
#define PWM_CHANNEL_OFFSET  ( PWM1_REG_BASE - PWM0_REG_BASE )

typedef struct PwmCtrlRegsS
{
	VUINT32	CTRL ;
	VUINT32 DUTY ;
	VUINT32 PERVAL ;
} PwmCtrlRegsT ;

// PWM errors.
#define ERR_PWM              0x00     // General PWM error.

/*
*******************************************************************************
*    External Declarations
*******************************************************************************
*/
extern UINT32 XsPwmReadPerval(UINT32 channel);
extern UINT32 XsPwmWritePerval(UINT32 channel, UINT32 value);

extern UINT32 XsPwmReadDuty(UINT32 channel);
extern UINT32 XsPwmWriteDuty(UINT32 channel, UINT32 value);
extern UINT32 XsPwmSetDutyCycle(UINT32 channel, UINT32 value);
extern UINT32 XsPwmSetDutyCycle(UINT32 channel, UINT32 value);
extern UINT32 XsPwmSetDutyCycle(UINT32 channel, UINT32 value);
extern UINT32 XsPwmSetDutyCycle(UINT32 channel, UINT32 value);

extern UINT32 XsPwmReadCtrl(UINT32 channel);
extern UINT32 XsPwmWriteCtrl(UINT32 channel, UINT32 value);
extern UINT32 XsPwmSetCtrlPrescale(UINT32 channel, UINT32 value);
extern UINT32 XsPwmSetCtrlAbruptShutdown(UINT32 channel);
extern UINT32 XsPwmSetCtrlGracefulShutdown(UINT32 channel);

#endif /* _XSPWM_H */