📄 i2c.c
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/******************************************************************************
**
** COPYRIGHT (C) 2000, 2001 Intel Corporation.
**
** This software as well as the software described in it is furnished under
** license and may only be used or copied in accordance with the terms of the
** license. The information in this file is furnished for informational use
** only, is subject to change without notice, and should not be construed as
** a commitment by Intel Corporation. Intel Corporation assumes no
** responsibility or liability for any errors or inaccuracies that may appear
** in this document or any software that may be provided in association with
** this document.
** Except as permitted by such license, no part of this document may be
** reproduced, stored in a retrieval system, or transmitted in any form or by
** any means without the express written consent of Intel Corporation.
**
** FILENAME: i2c.c
**
**
** LAST MODIFIED: $Modtime: 9/17/03 9:50a $
******************************************************************************/
#include <stdio.h>
#include "DRV_i2c.h"
#include "i2c.h"
#include "xllp_intc.h"
/*
* Initialization to use I2C bus
*
* PARAMETERS:
* unsigned int - Default slave device id for Cotulla
*
* RETURNS:
*/
XLLP_UINT32_T i2c_write(P_POST_I2C_T I2C_regs, P_XLLP_INTC_T int_regs, pI2C_TX seq)
{
XLLP_INT32_T errorLog=0, i=0;
XLLP_UINT32_T time_out;
if((errorLog = PostI2cSetupWrite(I2C_regs, int_regs, seq)) != XLLP_FALSE)
return(XLLP_TRUE);
/* Load the I2C Data Buffer Register with device id */
// this is simulating a interrupt routine
for(time_out=I2C_TIMEOUT;time_out!=0;time_out--)
{
if( ((int_regs->icpr & XLLP_BIT_6 ) == XLLP_BIT_6)||((int_regs->icpr & XLLP_BIT_18 ) == XLLP_BIT_18))
{
errorLog=PostI2cTxEmpty(I2C_regs);
break;
}
if (time_out == 0) return(XLLP_TRUE);
}
// this is the end of the simulated interrupt routine
/* Clear ICR START and TRANSFER bit. The TRANSFER bit should be self
* clearing but I'll make sure it is cleared anyway
*/
I2C_regs->ICR &= (~(POST_ICR_START | POST_ICR_STOP | POST_ICR_TB));
for(i=0;i<seq->data_len;i++)
{
if((errorLog = PostI2cWrite(I2C_regs, seq, i, POST_I2C_STOP)) != XLLP_FALSE)
return(XLLP_TRUE);
for(time_out=I2C_TIMEOUT;time_out!=0;time_out--)
{
if( ((int_regs->icpr & XLLP_BIT_6 ) == XLLP_BIT_6)||((int_regs->icpr & XLLP_BIT_18 ) == XLLP_BIT_18))
{
errorLog=PostI2cTxEmpty(I2C_regs);
break;
}
if (time_out == 0) return(XLLP_TRUE);
}
}
return(errorLog);
}
XLLP_UINT32_T i2c_read(P_POST_I2C_T i2c_regs, P_XLLP_INTC_T int_regs, pI2C_TX seq, P_XLLP_UINT8_T rx_data, XLLP_UINT32_T rx_data_len)
{
XLLP_UINT32_T time_out;
XLLP_INT32_T ret = 0; /* success */
XLLP_INT32_T errorLog=0, i=0;
/* Write command */
if((ret = i2c_write(i2c_regs,
int_regs,
seq)) != XLLP_FALSE)
{
return(XLLP_TRUE);
}
if((ret = PostI2cSetupRead(i2c_regs,
int_regs,
seq)) != XLLP_FALSE)
{
return(XLLP_TRUE);
}
for(time_out=I2C_TIMEOUT;time_out!=0;time_out--)
{
if( ((int_regs->icpr & XLLP_BIT_6 ) == XLLP_BIT_6)||((int_regs->icpr & XLLP_BIT_18 ) == XLLP_BIT_18))
{
errorLog=PostI2cTxEmpty(i2c_regs);
break;
}
if (time_out == 0) return(XLLP_TRUE);
}
/* Clear ICR START and TRANSFER bit. The TRANSFER bit should be self
* clearing but I'll make sure it is cleared anyway
*/
i2c_regs->ICR &= (~(POST_ICR_START| POST_ICR_TB| POST_ICR_STOP|POST_ICR_ACKNACK));
for(i=0;i<rx_data_len;i++)
{
if(PostI2cRead(i2c_regs, seq, i, rx_data, rx_data_len) != XLLP_FALSE)
return(XLLP_TRUE);
for(time_out=I2C_TIMEOUT;time_out!=0;time_out--)
{
if( ((int_regs->icpr & XLLP_BIT_6 ) == XLLP_BIT_6)||((int_regs->icpr & XLLP_BIT_18 ) == XLLP_BIT_18))
{
errorLog=PostI2cRxFull(i2c_regs);
break;
}
if (time_out == 0) return(XLLP_TRUE);
}
}
return XLLP_FALSE;
}
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