drv_i2c.h

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/******************************************************************************
**
**  COPYRIGHT (C) 2000, 2001 Intel Corporation.
**
**  This software as well as the software described in it is furnished under
**  license and may only be used or copied in accordance with the terms of the
**  license. The information in this file is furnished for informational use
**  only, is subject to change without notice, and should not be construed as
**  a commitment by Intel Corporation. Intel Corporation assumes no
**  responsibility or liability for any errors or inaccuracies that may appear
**  in this document or any software that may be provided in association with
**  this document.
**  Except as permitted by such license, no part of this document may be
**  reproduced, stored in a retrieval system, or transmitted in any form or by
**  any means without the express written consent of Intel Corporation.
**
**  LAST MODIFIED:  $Modtime: 9/17/03 9:45a $
******************************************************************************/
#include "xllp_intc.h"
#include "xllp_clkmgr.h"
#include "xllp_gpio.h"
#include "xllp_defs.h"

#ifndef __POST_I2C_H
#define __POST_I2C_H


/**************************
 * I2C Bus Interface Unit *
 **************************/
// note offset at 0x4030_16xx for standard i2c physical

typedef struct 
{
    XLLP_VUINT32_T IBMR;         /* Bus monitor register */
	XLLP_UINT32_T RESERVED1;	/* addr. offset 0x84-0x88 */
	XLLP_VUINT32_T IDBR;			/* Data buffer Register */
  	XLLP_UINT32_T RESERVED2;	/* addr. offset 0x8C-0x90*/
  	XLLP_VUINT32_T ICR;			/* Global Control Register */
  	XLLP_UINT32_T RESERVED3;	/* addr. offset 0x94-0x98 */
  	XLLP_VUINT32_T ISR;			/* Status Register*/
    XLLP_UINT32_T RESERVED4;	/* addr. offset 0x9C-0xA0 */
  	XLLP_VUINT32_T ISAR;			/* Slave address register */

} POST_I2C_T, *P_POST_I2C_T;

// note offset at 0x40F0_01xx  for power i2c at physical
typedef struct 
{
    XLLP_VUINT32_T PIBMR;         /* Bus monitor register */
	XLLP_UINT32_T RESERVED1;	/* addr. offset 0x84-0x88 */
	XLLP_VUINT32_T PIDBR;			/* Data buffer Register */
  	XLLP_UINT32_T RESERVED2;	/* addr. offset 0x8C-0x90*/
  	XLLP_VUINT32_T PICR;			/* Global Control Register */
  	XLLP_UINT32_T RESERVED3;	/* addr. offset 0x94-0x98 */
  	XLLP_VUINT32_T PISR;			/* Status Register*/
    XLLP_UINT32_T RESERVED4;	/* addr. offset 0x9C-0xA0 */
  	XLLP_VUINT32_T PISAR;			/* Slave address register */

} POST_PI2C_T, *P_POST_PI2C_T;


/*  bus monitor register */
#define	POST_IBMR_SDA		XLLP_BIT_0  /* reflects the status of SDA pin */
#define	POST_IBMR_SCL		XLLP_BIT_1 /* reflects the status of SCL pin */

/* data buffer regiter mask */
#define	POST_IDBR_ADDR		0xFF;  /*buffer for I2C bus send/receive data */
#define	POST_IDBR_MODE		XLLP_BIT_0	
/* Control Register */
#define	POST_ICR_START		XLLP_BIT_0 /* 1:send a Start condition to the I2C when in master mode */
#define	POST_ICR_STOP		XLLP_BIT_1 /* 1:send a Stop condition after next data byte transferred on I2C bus in master mode */
#define	POST_ICR_ACKNACK	XLLP_BIT_2  /* Ack/Nack control: 1:Nack, 0:Ack (negative or positive pulse) */
#define	POST_ICR_TB			XLLP_BIT_3  /* 1:send/receive byte, 0:cleared by I2C unit when done */
#define	POST_ICR_MA			XLLP_BIT_4  /* 1:I2C sends STOP w/out data permission, 0:ICR bit used only */
#define	POST_ICR_SCLEA		XLLP_BIT_5  /* I2C clock output: 1:Enabled, 0:Disabled. ICCR configured before ! */
#define	POST_ICR_UIE		XLLP_BIT_6 /* I2C unit: 1:Enabled, 0:Disabled */
#define	POST_ICR_GCD		XLLP_BIT_7  /* General Call: 1:Disabled, 0:Enabled */
#define	POST_ICR_ITEIE		XLLP_BIT_8  /* 1: IDBR Transmit Empty Interrupt Enable */
#define	POST_ICR_DRFIE		XLLP_BIT_9  /* 1: IDBR Receive Full Interrupt Enable */
#define	POST_ICR_BEIE		XLLP_BIT_10  /* 1: Bus Error Interrupt Enable */
#define	POST_ICR_SSDIE		XLLP_BIT_11 /* 1: Slave Stop Detected Interrupt Enable */
#define	POST_ICR_ALDIE		XLLP_BIT_12  /* 1: Arbitration Loss Detected Interrupt Enable */
#define	POST_ICR_SADIE		XLLP_BIT_13  /* 1: Slave Address Detected Interrupt Enable */
#define	POST_ICR_UR			XLLP_BIT_14  /* 1: I2C unit reset */
#define POST_ICR_FM   		XLLP_BIT_15 /* 1: Fast mode - 400 KBit/sec. operation. Default is 100 KBit/sec */

/* Status Register */
#define	POST_ISR_RWM		XLLP_BIT_0  /* 1: I2C in master receive = slave transmit mode */
#define	POST_ISR_ACKNACK	XLLP_BIT_1  /* 1: I2C received/sent a Nack, 0: Ack */
#define	POST_ISR_UB			XLLP_BIT_2  /* 1: Processor's I2C unit busy */
#define	POST_ISR_IBB		XLLP_BIT_3  /* 1: I2C bus busy. Processor's I2C unit not involved */
#define	POST_ISR_SSD		XLLP_BIT_4  /* 1: Slave Stop detected (when in slave mode: receive or transmit) */
#define	POST_ISR_ALD		XLLP_BIT_5  /* 1: Arbitration Loss Detected */
#define	POST_ISR_ITE		XLLP_BIT_6  /* 1: Transfer finished on I2C bus. If enabled in ICR, interrupt signaled */
#define	POST_ISR_IRF		XLLP_BIT_7  /* 1: IDBR received new byte from I2C bus. If ICR, interrupt signaled */
#define	POST_ISR_GCAD		XLLP_BIT_8  /* 1: I2C unit received a General Call address */
#define	POST_ISR_SAD		XLLP_BIT_9  /* 1: I2C unit detected a 7-bit address matching the general call or ISAR */
#define	POST_ISR_BED		XLLP_BIT_10  /* Bit set by unit when a Bus Error detected */

/*  slave address mask */
#define	POST_ISAR_ADDR		0x7F;	/*  7-bit(6:0) add to which I2C unit responses to in slave/receive mode*/

#define POST_ICR_INIT_VALUE (POST_ICR_GCD|POST_ICR_UIE|POST_ICR_SCLEA)

#define POST_I2C_NO_STOP     0    /* Don't issue stop bit */
#define POST_I2C_STOP        1    /* Issue stop bit */

/* struct that contains the I2C transmit data */

typedef struct  _i2c_tx {
  XLLP_UINT8_T  dev_id;    /* Slave address */
  XLLP_UINT32_T  data_len;  /* Length of trailing data transmit */
  XLLP_UINT8_T *data;      /* Trailing data to transmit */
} I2C_TX, *pI2C_TX;


/* Processor I2C Device ID */
#define POST_I2C_SLAVE_ID 0x4E  /* 0100_111x */ /* The Phillips spec says it must be a value between 0001_000xB and 1110_111xB */

XLLP_BOOL_T PostI2cInit(P_POST_I2C_T I2C_regs, P_XLLP_GPIO_T gpio, P_XLLP_CLKMGR_T clkMgr, XLLP_UINT32_T dev_id);
XLLP_BOOL_T PostI2cRxFull(P_POST_I2C_T i2c_regs);
XLLP_BOOL_T PostI2cTxEmpty(P_POST_I2C_T i2c_regs);

XLLP_BOOL_T PostI2cSetupWrite(P_POST_I2C_T I2C_regs, P_XLLP_INTC_T int_regs,
								pI2C_TX seq);
XLLP_BOOL_T PostI2cWrite(P_POST_I2C_T i2c_regs, pI2C_TX seq, 
								XLLP_UINT32_T ByteNum, XLLP_UINT32_T stop_bit);

XLLP_BOOL_T PostI2cSetupRead(P_POST_I2C_T i2c_regs, P_XLLP_INTC_T int_regs, pI2C_TX seq);

XLLP_BOOL_T PostI2cRead(P_POST_I2C_T I2C_regs, pI2C_TX seq, XLLP_UINT32_T ByteNum, 
						P_XLLP_UINT8_T rx_data, XLLP_UINT32_T rx_data_len);

XLLP_BOOL_T PostI2cStopRead(P_POST_I2C_T i2c_regs);



#endif /* XLLP_I2C_H */