xsssp.h

优龙YLP270开发板 光盘自带的BIOS和实验例程源码 强烈推荐

/******************************************************************************
**
**  COPYRIGHT (C) 2000, 2001 Intel Corporation.
**
**  This software as well as the software described in it is furnished under 
**  license and may only be used or copied in accordance with the terms of the 
**  license. The information in this file is furnished for informational use 
**  only, is subject to change without notice, and should not be construed as 
**  a commitment by Intel Corporation. Intel Corporation assumes no 
**  responsibility or liability for any errors or inaccuracies that may appear 
**  in this document or any software that may be provided in association with 
**  this document. 
**  Except as permitted by such license, no part of this document may be 
**  reproduced, stored in a retrieval system, or transmitted in any form or by 
**  any means without the express written consent of Intel Corporation. 
**
**  FILENAME:       xsssp.h
**
**  PURPOSE:        Header file for the SSP1, SSP2, and SSP3 Serial Ports
**
**  $Modtime: 7/17/03 1:01p $
**  EAS VERSION:    2.1
******************************************************************************/

#ifndef _xsssp_h
#define _xsssp_h

/*
************************************************************************************
*                           CONSTANTS 
************************************************************************************
*/

#ifdef SSP_GLOBALS
#define EXTRN
#else
#define EXTRN extern
#endif

// Masks for SSP Registers

// SSP Control Register 0 (SSCR0) definitions
#define SSP_SSCR0_DSS_MASK  0xf        // Use to read/clear the DSS field

#define SSP_SSCR0_DSS_4         ( 0x3u << 0 )  //  4-bit data 
#define SSP_SSCR0_DSS_5         ( 0x4u << 0 )  //  5-bit data 
#define SSP_SSCR0_DSS_6         ( 0x5u << 0 )  //  6-bit data 
#define SSP_SSCR0_DSS_7         ( 0x6u << 0 )  //  7-bit data 
#define SSP_SSCR0_DSS_8         ( 0x7u << 0 )  //  8-bit data 
#define SSP_SSCR0_DSS_9         ( 0x8u << 0 )  //  9-bit data 
#define SSP_SSCR0_DSS_10        ( 0x9u << 0 )  // 10-bit data 
#define SSP_SSCR0_DSS_11        ( 0xau << 0 )  // 11-bit data 
#define SSP_SSCR0_DSS_12        ( 0xbu << 0 )  // 12-bit data 
#define SSP_SSCR0_DSS_13        ( 0xcu << 0 )  // 13-bit data 
#define SSP_SSCR0_DSS_14        ( 0xdu << 0 )  // 14-bit data 
#define SSP_SSCR0_DSS_15        ( 0xeu << 0 )  // 15-bit data 
#define SSP_SSCR0_DSS_16        ( 0xfu << 0 )  // 16-bit data 

#define SSP_SSCR0_FRF_SPI       ( 0x0u << 4 )  // Serial Peripheral Interface 
#define SSP_SSCR0_FRF_SSP       ( 0x1u << 4 )  // TI Sync. Serial Protocol
#define SSP_SSCR0_FRF_MICWIRE   ( 0x2u << 4 )  // National Microwire
#define SSP_SSCR0_FRF_PSP       ( 0x3u << 4 )  // Programmable Serial Protocol

#define SSP_SSCR0_ECS           ( 0x1u << 6 )  // External clock is used to create the SSP's SSPSCLK
#define SSP_SSCR0_SSE           ( 0x1u << 7 )  // SSP operation enabled
#define SSP_SSCR0_SCR_SHIFT     8             // Use to shift SCR                                               value
#define SSP_SSCR0_SCR_MASK      ( 0xfffu << SSP_SSCR0_SCR_SHIFT )  // Use to mask SCR                                               value

#define SSP_SSCR0_EDSS          ( 0x1u << 20 )  // Extended Data Size Select

#define SSP_SSCR0_NCS           ( 0x1u << 21 )  // Network Clock Select

// SSP Control Register 1 (SSCR1) definitions
#define SSP_SSCR1_RIE           ( 0x1u << 0 )  // Rx FIFO lvl int enabled
#define SSP_SSCR1_TIE           ( 0x1u << 1 )  // Tx FIFO lvl int enabled
#define SSP_SSCR1_LBM           ( 0x1u << 2 )  // Serial loopback enabled
#define SSP_SSCR1_SPO           ( 0x1u << 3 )  // IDLE state of SSPSCLK is Hi
#define SSP_SSCR1_SPH           ( 0x1u << 4 )  // SSPSCLK is inactive 1/2 cycle
                                               // at sart of and onw cycle at end of frame
#define SSP_SSCR1_MWDS          ( 0x1u << 5 )  // 16-bit command words

// Use the TFT mask and shift to set or clear
// the Transmit FIFO interrupt threshold value fields
#define SSP_SSCR1_TFT_SHFT      6
#define SSP_SSCR1_TFT_MASK      ( 0xfu << SSP_SSCR1_TFT_SHFT ) 

// Use the RFT mask and shift to set or clear
// the Receive FIFO interrupt threshold value fields
#define SSP_SSCR1_RFT_SHFT      10  
#define SSP_SSCR1_RFT_MASK      ( 0xfu << SSP_SSCR1_RFT_SHFT )
#define SSP_SSCR1_EFWR          ( 0x1u << 14 ) // FIFO W/R spec func enabled
#define SSP_SSCR1_STRF          ( 0x1u << 15 ) // Rx FIFO selected for reads/writes throught the SSDR
#define SSP_SSCR1_PINTE         ( 0x1u << 18 ) // Peripheral Trailing Byte Interrupt Enabled
#define SSP_SSCR1_TINTE         ( 0x1u << 19 ) // Rx Time-out Interrupt Enabled
#define SSP_SSCR1_RSRE          ( 0x1u << 20 ) // Rx Service Request Enabled
#define SSP_SSCR1_TSRE          ( 0x1u << 21 ) // Tx Service Request Enabled
#define SSP_SSCR1_TRAIL         ( 0x1u << 22 ) // Trailling Byte
#define SSP_SSCR1_RWOT          ( 0x1u << 23 ) // Receive w/o Transmit
#define SSP_SSCR1_SFRMDIR       ( 0x1u << 24 ) // SSP Frame Direction
#define SSP_SSCR1_SCLKDIR       ( 0x1u << 25 ) // SSP Serial Bit Rate Clock Direction
#define SSP_SSCR1_ECRB          ( 0x1u << 26 ) // Enable Clock Request B
#define SSP_SSCR1_ECRA          ( 0x1u << 27 ) // Enable Clock Request A
#define SSP_SSCR1_SCFR          ( 0x1u << 28 ) // Slave Clock Free Runing

// SSP Status Register (SSSR) definitions
#define SSP_SSSR_TNF            ( 0x1u << 2 )  // Tx FIFO not full
#define SSP_SSSR_RNE            ( 0x1u << 3 )  // Rx FIFO not empty
#define SSP_SSSR_BSY            ( 0x1u << 4 )  // SSP is currently transmitting
#define SSP_SSSR_TFS            ( 0x1u << 5 )  // Tx FIFO is at <= TFT Thresh
#define SSP_SSSR_RFS            ( 0x1u << 6 )  // Rx FIFO is at >= RFT Thresh
#define SSP_SSSR_ROR            ( 0x1u << 7 )  // Attempted write to full Rx FIFO

// Use the following for determining and manipulating Tx FIFO number of entries 
#define SSP_SSSR_TFL_SHIFT      8
#define SSP_SSSR_TFL_MASK       ( 0xfu << SSP_SSSR_TFL_SHIFT )   // Use to read/clear
                                                                // Number of entries
                                                                // in Tx FIFO

// Use the following for determining and manipulating Rx FIFO number of entries
#define SSP_SSSR_RFL_SHIFT      12
#define SSP_SSSR_RFL_MASK       ( 0xfu << SSP_SSSR_RFL_SHIFT )  // Use to read/clear
                                                                // Number of entries
                                                                // in Rx FIFO

#define SSP_SSSR_PINT           ( 0x1u << 18 )  // Trailing byte Interrupt
#define SSP_SSSR_TINT           ( 0x1u << 19 )  // Receiver Time-out Interrupt
#define SSP_SSSR_EOC            ( 0x1u << 20 )  // End of Chain
#define SSP_SSSR_TUR            ( 0x1u << 21 )  // Tx FIFO under run

// SSP Interrupt Test Register (SSITR) definitions
#define SSP_SSITR_TTFS          ( 0x1u << 5 )  // Test Tx FIFO service request
#define SSP_SSITR_TRFS          ( 0x1u << 6 )  // Test Rx FIFO service request
#define SSP_SSITR_TROR          ( 0x1u << 7 )  // Test Rx FIFO overrun

// SSP Time Out Register definitions.
#define SSP_SSTO_TIMEOUT_SHFT    0            // Timeout
#define SSP_SSTO_TIMEOUT_MASK    (0x00FFFFFFU << SSP_SSTO_TIMEOUT_SHFT)

// SSP Programmable Serial Prototocl Register definitions.
#define SSP_SSPSP_SCMODE_SHFT    0            // Serial bit-rate Clock Mode
#define SSP_SSPSP_SCMODE_MASK    (0x3U << SSP_SSPSP_SCMODE_SHFT)
#define SSP_SSPSP_SFRMP          (0x1U << 2)  // Serial Frame Polarity
#define SSP_SSPSP_ETDS           (0x1U << 3)  // End of Transfer Data State
#define SSP_SSPSP_STRTDLY_SHFT   4            // Start Delay
#define SSP_SSPSP_STRTDLY_MASK   (0x7U << SSP_SSPSP_STRTDLY_SHFT)
#define SSP_SSPSP_DMYSTRT_SHFT   7            // Dymmy Start
#define SSP_SSPSP_DMYSTRT_MASK   (0x3U << SSP_SSPSP_DMYSTRT_SHFT)
#define SSP_SSPSP_SFRMDLY_SHFT   9            // Serial Frame Delay
#define SSP_SSPSP_SFRMDLY_MASK   (0x7FU << SSP_SSPSP_SFRMDLY_SHFT)
#define SSP_SSPSP_SFRMWDTH_SHFT  16           // Serial Frame Width
#define SSP_SSPSP_SFRMWDTH_MASK   (0x3FU << SSP_SSPSP_SFRMWDTH_SHFT)
#define SSP_SSPSP_DMYSTOP_SHFT   25           // Dummy Stop
#define SSP_SSPSP_DMYSTOP_MASK   (0x3U << SSP_SSPSP_DMYSTOP_SHFT)

#define SSP1_REG_BASE           ( 0x41000000 )
#define SSP2_REG_BASE           ( 0x41700000 )
#define SSP3_REG_BASE           ( 0x41900000 )

#define NOT_USED                0

#define NUM_BUF_DEFAULT_SSP     2   
#define BUFF_SIZE_DEFAULT_SSP   64  
#define XFER_LEN_DEFAULT_SSP    128

//    Sub-location codes - 8 bits max - 253 possible sub-location codes.
#define ERR_S_XSSSP_HWSETUP              0x01 // HWSetup
#define ERR_S_XSSSP_INT_HANDLER          0x02 // Register Interrupt Handler
#define ERR_S_XSSSP_TRANSMIT             0x03 // Transmit function
#define ERR_S_XSSSP_RECEIVE              0x04 // Receive function
#define ERR_S_XSSSP_STATIC_LOOPBACK      0x05 // Static loopback function
#define ERR_S_XSSSP_INV_DEV              0x06 // SW Init
#define ERR_S_XSSSP_DMA_LOOPBACK         0x07 // DMA Loopback
#define ERR_S_XSSSP_INVALID              0x08 // Invalid setup.

// Error sub-location codes used by the tests
#define ERR_TS_XSSSP_LOOPSINGLE         0x80 // SspLoopbackSingle
#define ERR_TS_XSSSP_LOOPSTATIC         0x81 // PostSspStaticLoop
#define ERR_TS_XSSSP_DMA_LOOPBACK       0x82 // SSP DMA Loopback
#define ERR_TS_XSSSP_DMA_INTERRUPT      0x83 // SSP DMA Interrupt


/*
************************************************************************************
*                           DATA TYPES                
************************************************************************************
*/

// SSP Registers structure 
typedef struct SspRegS
{
    VUINT SSCR0;    // SSP Control Register 0
    VUINT SSCR1;    // SSP Control Register 1
    VUINT SSSR;     // SSP Status Register
    VUINT SSITR;    // SSP Interrupt Test Register
    VUINT SSDR;     // SSP Data Write/Read Register