xsgpioplatform.h

优龙YLP270开发板 光盘自带的BIOS和实验例程源码 强烈推荐

/******************************************************************************
**
**  COPYRIGHT (C) 2002 Intel Corporation.
**
**  This software as well as the software described in it is furnished under
**  license and may only be used or copied in accordance with the terms of the
**  license. The information in this file is furnished for informational use
**  only, is subject to change without notice, and should not be construed as
**  a commitment by Intel Corporation. Intel Corporation assumes no
**  responsibility or liability for any errors or inaccuracies that may appear
**  in this document or any software that may be provided in association with
**  this document.
**  Except as permitted by such license, no part of this document may be
**  reproduced, stored in a retrieval system, or transmitted in any form or by
**  any means without the express written consent of Intel Corporation.
**
**  FILENAME:       XsGpioPlatform.h
**
**  PURPOSE:        Platform-specific constants and table definitions for the
**                  use of the main processor on-board General Purpose
**                  Input/Output devices' driver.  Mostly the default
**                  initialization tables.
**
**  Needs:          XsGpio.h and XsGpioApi.h
**
**  Valid for    :  Bulverde processor
**               :  Mainstone platform
**
**  EAS VERSION  :  2.0
**
**  $Modtime: 7/17/03 1:01p $
******************************************************************************/

/*
*******************************************************************************
    Aliases for pin levels
*******************************************************************************
*/

#define XS_GPIO_PIN_LEVEL_X         XS_GPIO_PIN_LEVEL_0 // Don't-care level for init
#define XS_GPIO_PIN_LEVEL_UNKNOWN   XS_GPIO_PIN_LEVEL_0 // Don't-know, can't-guess level for init
#define XS_GPIO_PIN_LEVEL_ASSUMED_1   XS_GPIO_PIN_LEVEL_1 // Don't-know, guess high level for init

/*
*******************************************************************************
    Usage #defines for defaultCategory fields in XsGpioDefaultConfigTable
    - Must be defined as one of the XsGpioInitCategoryT enums.
    - Purpose is to provide an indication of the usage for each GPIO pin,
        plus allow a simple way to exclude DM access to certain pins for
        debug builds which assume that a debug monitor "owns" them.
*******************************************************************************
*/

//    Symbol to use in          Corresponding
//  defaultCategory field     XsGpioInitCategory

#define ___XSG_UNKNOWN___      GPIO_INIT_NO   // Early devel, placeholder
#define _XSG_AC97              GPIO_INIT_ALT

#ifdef BOOTABLE
#define _XSG_BTUART            GPIO_INIT_ALT  // BlueTooth UART
#else       // debug build, assume Angel, check switch setting for OK to init
#define _XSG_BTUART            GPIO_INIT_CHK_BT   // BlueTooth UART
#endif

#define _XSG_CARD              GPIO_INIT_ALT  // Normally, PCMCIA card space
#define _XSG_CLK_32_KHZ_OUT    GPIO_INIT_ALT  // 32 KHz Clock
#define _XSG_CLK_48_MHZ_0UT    GPIO_INIT_ALT  // 48 MHz clock
#define _XSG_EXT_BUS_RDY       GPIO_INIT_ALT

#ifdef BOOTABLE
#define _XSG_FFUART            GPIO_INIT_ALT  // Full Featured UART
#else       // debug build, assume Angel, check switch setting for OK to init
#define _XSG_FFUART            GPIO_INIT_CHK_FF   // Full Featured UART
#endif

#define _XSG_GP_RST            GPIO_INIT_ALT  // Pin 1, always.
#define _XSG_GPIO              GPIO_INIT_GPIO // Unspecified GPIO usage
#define _XSG_I2S               GPIO_INIT_ALT
#define _XSG_ICP               GPIO_INIT_ALT  // Infrared Communications Port
#define _XSG_LCD               GPIO_INIT_ALT
    // Memory Controller Alternate Bus Master Request or grant
#define _XSG_ALT_BUS_MSTR      GPIO_INIT_ALT
#define _XSG_MMC               GPIO_INIT_ALT
#define _XSG_NCS_1             GPIO_INIT_ALT  // nCS[1]
#define _XSG_NCS_2             GPIO_INIT_ALT  // nCS[2]
#define _XSG_NCS_3             GPIO_INIT_ALT  // nCS[3]
#define _XSG_NCS_4             GPIO_INIT_ALT  // nCS[4]
#define _XSG_NCS_5             GPIO_INIT_ALT  // nCS[5]
#define _XSG_PWM_0_OUT         GPIO_INIT_ALT
#define _XSG_PWM_1_OUT         GPIO_INIT_ALT
#define _XSG_RTC_1_HZ          GPIO_INIT_ALT  // real time clock (1Hz)
#define _XSG_SSP               GPIO_INIT_ALT  // SSP
#define _XSG_STUART            GPIO_INIT_ALT  // Standard UART

/*
*******************************************************************************
  Default GPIO Configuration Table for standalone daughtercard.
*******************************************************************************
*/

XsGpioDefaultEntryT XsGpioDfltCfgTblNoExpBd [XS_GPIO_PIN_COUNT]=
{
     // GPIO ID, schematic symbol, usage in system
// defaultCategory,     altFunctionSelector,  direction,        initialLevel,         simulatedLevelInt

    //  00 - GPIO[0]
{_XSG_GPIO,            XS_GPIO_ALT_FUNC_GPIO, XS_GPIO_DIR_IN,  XS_GPIO_PIN_LEVEL_X,       TRUE},
    //  01 - GPIO[1]
{_XSG_GPIO,            XS_GPIO_ALT_FUNC_GPIO, XS_GPIO_DIR_IN,  XS_GPIO_PIN_LEVEL_X,       FALSE},
    //  02 - GPIO[2]
{_XSG_GPIO,            XS_GPIO_ALT_FUNC_GPIO, XS_GPIO_DIR_IN,  XS_GPIO_PIN_LEVEL_X,       FALSE},
    //  03 - GPIO[3]
{_XSG_GPIO,            XS_GPIO_ALT_FUNC_GPIO, XS_GPIO_DIR_IN,  XS_GPIO_PIN_LEVEL_X,       FALSE},
    //  04 - GPIO[4]
{_XSG_GPIO,            XS_GPIO_ALT_FUNC_GPIO, XS_GPIO_DIR_IN,  XS_GPIO_PIN_LEVEL_X,       FALSE},
    //  05 - GPIO[5]
{_XSG_GPIO,            XS_GPIO_ALT_FUNC_GPIO, XS_GPIO_DIR_IN,  XS_GPIO_PIN_LEVEL_X,       FALSE},
    //  06 - GPIO[6]
{_XSG_GPIO,            XS_GPIO_ALT_FUNC_GPIO, XS_GPIO_DIR_IN,  XS_GPIO_PIN_LEVEL_X,       FALSE},
    //  07 - GPIO[7]
{_XSG_GPIO,            XS_GPIO_ALT_FUNC_GPIO, XS_GPIO_DIR_IN,  XS_GPIO_PIN_LEVEL_X,       FALSE},
    //  08 - GPIO[8]
{_XSG_GPIO,            XS_GPIO_ALT_FUNC_GPIO, XS_GPIO_DIR_IN,  XS_GPIO_PIN_LEVEL_X,       FALSE},
    //  09 - GPIO[9]
{_XSG_GPIO,            XS_GPIO_ALT_FUNC_GPIO, XS_GPIO_DIR_IN,  XS_GPIO_PIN_LEVEL_X,       FALSE},
    //  10 - GPIO[10]: 32 KHz oscillator output
{_XSG_CLK_32_KHZ_OUT,  XS_GPIO_ALT_FUNC_GPIO, XS_GPIO_DIR_IN,  XS_GPIO_PIN_LEVEL_X,       FALSE},
    //  11 - 48M_CLK: 48 MHz oscillator output
{_XSG_CLK_48_MHZ_0UT,  XS_GPIO_ALT_FUNC_3,    XS_GPIO_DIR_OUT, XS_GPIO_PIN_LEVEL_X,       FALSE},
    //  12 - GPIO[12]: nWP
{_XSG_GPIO,            XS_GPIO_ALT_FUNC_GPIO, XS_GPIO_DIR_OUT, XS_GPIO_PIN_LEVEL_0,       FALSE},
    //  13 - MBGNT: Memory controller grant
{_XSG_ALT_BUS_MSTR,    XS_GPIO_ALT_FUNC_2,    XS_GPIO_DIR_OUT, XS_GPIO_PIN_LEVEL_UNKNOWN, FALSE},
    //  14 - MBREQ: Memory controller alternate bus master request
{_XSG_ALT_BUS_MSTR,    XS_GPIO_ALT_FUNC_1,    XS_GPIO_DIR_IN,  XS_GPIO_PIN_LEVEL_X,       FALSE},
    //  15 - nCS1: Chip select 1
{_XSG_NCS_1,           XS_GPIO_ALT_FUNC_2,    XS_GPIO_DIR_OUT, XS_GPIO_PIN_LEVEL_1,       FALSE},
    //  16 - PWM0: Pulse width modulation signal channel 0
{_XSG_PWM_0_OUT,       XS_GPIO_ALT_FUNC_2,    XS_GPIO_DIR_OUT, XS_GPIO_PIN_LEVEL_X,       FALSE},
    //  17 - PWM1: Pulse width modulation signal channel 1
{_XSG_PWM_1_OUT,       XS_GPIO_ALT_FUNC_2,    XS_GPIO_DIR_OUT, XS_GPIO_PIN_LEVEL_X,       FALSE},
    //  18 - RDY: Variable latency I/O Device Ready
{_XSG_EXT_BUS_RDY,     XS_GPIO_ALT_FUNC_1,    XS_GPIO_DIR_IN,  XS_GPIO_PIN_LEVEL_X,       FALSE},
    //  19 - GP19 (?): Unused
{_XSG_GPIO,            XS_GPIO_ALT_FUNC_GPIO, XS_GPIO_DIR_IN,  XS_GPIO_PIN_LEVEL_X,       FALSE},
    //  20 - GP20 (?): Unused
{_XSG_GPIO,            XS_GPIO_ALT_FUNC_GPIO, XS_GPIO_DIR_IN,  XS_GPIO_PIN_LEVEL_X,       FALSE},
    //  21 - GP21 (?): Unused
{_XSG_GPIO,            XS_GPIO_ALT_FUNC_GPIO, XS_GPIO_DIR_IN,  XS_GPIO_PIN_LEVEL_X,       FALSE},
    //  22 - GP22 (?): Unused
{_XSG_GPIO,            XS_GPIO_ALT_FUNC_GPIO, XS_GPIO_DIR_IN,  XS_GPIO_PIN_LEVEL_X,       FALSE},
    //  23 - SSP_SCLK: Synchronus Serial Port Clock
{_XSG_SSP,             XS_GPIO_ALT_FUNC_2,    XS_GPIO_DIR_OUT, XS_GPIO_PIN_LEVEL_X,       FALSE},
    //  24 - SSP_SFRM: Synchronous Serial Port Frame
{_XSG_SSP,             XS_GPIO_ALT_FUNC_2,    XS_GPIO_DIR_OUT, XS_GPIO_PIN_LEVEL_X,       FALSE},
    //  25 - SSP_TXD: Synchronous Serial Port Transmit
{_XSG_SSP,             XS_GPIO_ALT_FUNC_2,    XS_GPIO_DIR_OUT, XS_GPIO_PIN_LEVEL_X,       FALSE},
    //  26 - SSP_RXD: Synchronous Serial Port Receive
{_XSG_SSP,             XS_GPIO_ALT_FUNC_1,    XS_GPIO_DIR_IN,  XS_GPIO_PIN_LEVEL_X,       FALSE},
    //  27 - SSP_EXTCLK: Unused, Synchronous Serial Port External Clock
{_XSG_SSP,             XS_GPIO_ALT_FUNC_GPIO, XS_GPIO_DIR_IN,  XS_GPIO_PIN_LEVEL_X,       FALSE},
    //  28 - SAC_BITCLK: AC-Link Bit Clock
{_XSG_AC97,            XS_GPIO_ALT_FUNC_1,    XS_GPIO_DIR_IN,  XS_GPIO_PIN_LEVEL_X,       FALSE},