📄 xsac97ctrl.c
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/******************************************************************************
**
** COPYRIGHT (C) 2000, 2001 Intel Corporation.
**
** This software as well as the software described in it is furnished under
** license and may only be used or copied in accordance with the terms of the
** license. The information in this file is furnished for informational use
** only, is subject to change without notice, and should not be construed as
** a commitment by Intel Corporation. Intel Corporation assumes no
** responsibility or liability for any errors or inaccuracies that may appear
** in this document or any software that may be provided in association with
** this document.
** Except as permitted by such license, no part of this document may be
** reproduced, stored in a retrieval system, or transmitted in any form or by
** any means without the express written consent of Intel Corporation.
**
** FILENAME: XsAc97Ctrl.c
**
** PURPOSE: Driver for the main processor's on-board AC'97 Controller
** device. Includes initialization, API and support
** functions.
**
** Valid for : Subset of AC '97 Rev 2.1
**
** Valid for : Cotulla processor
**
** EAS VERSION : 2.1
**
** $Modtime: 7/17/03 1:01p $
******************************************************************************/
#define _DEFINING_XSAC97CTRL
#include "string.h"
#include "systypes.h"
#include "dm_errors.h"
#include "timedelays.h"
#include "XsCp15.h"
#include "XsIntCtrlApi.h"
#include "XsClkMgr.h"
#include "Ac97MixerRegsApi.h"
#include "XsAc97CtrlApi.h"
#include "XsAc97Ctrl.h"
#include "DM_Debug.h"
/*
*******************************************************************************
Functions in standard driver API of main processor on-board AC'97 Controller
*******************************************************************************
*/
/*
*******************************************************************************
*
* FUNCTION: XsAc97CtrlSWInit
*
* DESCRIPTION: Init context structure and private table.
*
* INPUT PARAMETERS: None
*
* RETURNS: None
*
* GLOBAL EFFECTS: None
*
* ASSUMPTIONS:
*
* CALLS: XsAc97CtrlSetStatusEntry
*
* CALLED BY:
*
* PROTOTYPE: void XsAc97CtrlSWInit (void);
*
*******************************************************************************
*/
void XsAc97CtrlSWInit (void)
{
// Zero AC'97 Controller context structure
memset (&XsAc97CtrlContext, 0, sizeof(XsAc97CtrlContext));
//
// Initialize the status indicators table, which also serves as the
// registered interrupt (callback) processing table
// All interrupt types set to disabled, with no registered handler or param
//
// CODEC GPI Status Change
XsAc97CtrlSetStatusEntry (&XsAc97CtrlStatusTable [XS_AC97CTRL_STAT_GSCI],
FALSE, // intIsSupported
&XsAc97CtrlRegsP->GCR, // enableRegisterP
XS_AC97CTRL_GCR_GIE_SH, // enableBitShift
1u, // reportBitMaskGsr
XS_AC97CTRL_GSR_GSCI_SH, // reportBitShiftGsr
&XsAc97CtrlRegsP->GSR, // clearRegisterP
XS_AC97CTRL_GSR_GSCI_SH); // clearBitShift
// MODEM In
XsAc97CtrlSetStatusEntry (&XsAc97CtrlStatusTable [XS_AC97CTRL_STAT_MDM_IN],
FALSE, // intIsSupported
&XsAc97CtrlRegsP->MICR, // enableRegisterP
XS_AC97CTRL_FIFO_ERR_CTRL_SHFT, // enableBitShift
1u, // reportBitMaskGsr
XS_AC97CTRL_GSR_MIINT_SH, // reportBitShiftGsr
&XsAc97CtrlRegsP->MISR, // clearRegisterP
XS_AC97CTRL_FIFO_ERR_STAT_SHFT); // clearBitShift
// MODEM Out
XsAc97CtrlSetStatusEntry (&XsAc97CtrlStatusTable [XS_AC97CTRL_STAT_MDM_OUT],
FALSE, // intIsSupported
&XsAc97CtrlRegsP->MOCR, // enableRegisterP
XS_AC97CTRL_FIFO_ERR_CTRL_SHFT, // enableBitShift
1u, // reportBitMaskGsr
XS_AC97CTRL_GSR_MOINT_SH, // reportBitShiftGsr
&XsAc97CtrlRegsP->MOSR, // clearRegisterP
XS_AC97CTRL_FIFO_ERR_STAT_SHFT); // clearBitShift
// PCM In
XsAc97CtrlSetStatusEntry (&XsAc97CtrlStatusTable [XS_AC97CTRL_STAT_PCM_IN],
TRUE, // intIsSupported
&XsAc97CtrlRegsP->PICR, // enableRegisterP
XS_AC97CTRL_FIFO_ERR_CTRL_SHFT, // enableBitShift
1u, // reportBitMaskGsr
XS_AC97CTRL_GSR_PIINT_SH, // reportBitShiftGsr
&XsAc97CtrlRegsP->PISR, // clearRegisterP
XS_AC97CTRL_FIFO_ERR_STAT_SHFT); // clearBitShift
// PCM Out
XsAc97CtrlSetStatusEntry (&XsAc97CtrlStatusTable [XS_AC97CTRL_STAT_PCM_OUT],
TRUE, // intIsSupported
&XsAc97CtrlRegsP->POCR, // enableRegisterP
XS_AC97CTRL_FIFO_ERR_CTRL_SHFT, // enableBitShift
1u, // reportBitMaskGsr
XS_AC97CTRL_GSR_POINT_SH, // reportBitShiftGsr
&XsAc97CtrlRegsP->POSR, // clearRegisterP
XS_AC97CTRL_FIFO_ERR_STAT_SHFT); // clearBitShift
// Mic In
XsAc97CtrlSetStatusEntry (&XsAc97CtrlStatusTable [XS_AC97CTRL_STAT_MIC_IN],
TRUE, // intIsSupported
&XsAc97CtrlRegsP->MCCR, // enableRegisterP
XS_AC97CTRL_FIFO_ERR_CTRL_SHFT, // enableBitShift
1u, // reportBitMaskGsr
XS_AC97CTRL_GSR_MINT_SH, // reportBitShiftGsr
&XsAc97CtrlRegsP->MCSR, // clearRegisterP
XS_AC97CTRL_FIFO_ERR_STAT_SHFT); // clearBitShift
// Primary CODEC Ready
// Difficult to support via interrupt; special handling would be required
// in the ISR and in other parts of the code because the indication for
// this normal status cannot be cleared and the interrupt is level
// triggered, not edge (event) triggered.
XsAc97CtrlSetStatusEntry (&XsAc97CtrlStatusTable [XS_AC97CTRL_STAT_PCRDY],
FALSE, // intIsSupported
&XsAc97CtrlRegsP->GCR, // enableRegisterP
XS_AC97CTRL_GCR_PCRDY_IEN_SH, // enableBitShift
1u, // reportBitMaskGsr
XS_AC97CTRL_GSR_PCRDY_SH, // reportBitShiftGsr
NULL, // clearRegisterP: Can't clear
0 ); // clearBitShift: Can't clear
// Secondary CODEC Ready
// Difficult to support via interrupt; special handling would be required
// in the ISR and in other parts of the code because the indication for
// this normal status cannot be cleared and the interrupt is level
// triggered, not edge (event) triggered.
XsAc97CtrlSetStatusEntry (&XsAc97CtrlStatusTable [XS_AC97CTRL_STAT_SCRDY],
FALSE, // intIsSupported
&XsAc97CtrlRegsP->GCR, // enableRegisterP
XS_AC97CTRL_GCR_SCRDY_IEN_SH, // enableBitShift
1u, // reportBitMaskGsr
XS_AC97CTRL_GSR_SCRDY_SH, // reportBitShiftGsr
NULL, // clearRegisterP: Can't clear
0 ); // clearBitShift: Can't clear
// Primary Resume
XsAc97CtrlSetStatusEntry (&XsAc97CtrlStatusTable [XS_AC97CTRL_STAT_PCRSM],
FALSE, // intIsSupported
&XsAc97CtrlRegsP->GCR, // enableRegisterP
XS_AC97CTRL_GCR_PCRSM_IEN_SH, // enableBitShift
1u, // reportBitMaskGsr,
XS_AC97CTRL_GSR_PCRSM_SH, // reportBitShiftGsr
&XsAc97CtrlRegsP->GSR, // clearRegisterP
XS_AC97CTRL_GSR_PCRSM_SH ); // clearBitShift
// Secondary Resume
XsAc97CtrlSetStatusEntry (&XsAc97CtrlStatusTable [XS_AC97CTRL_STAT_SCRSM],
FALSE, // intIsSupported
&XsAc97CtrlRegsP->GCR, // enableRegisterP
XS_AC97CTRL_GCR_SCRSM_IEN_SH, // enableBitShift
1u, // reportBitMaskGsr,
XS_AC97CTRL_GSR_SCRSM_SH, // reportBitShiftGsr
&XsAc97CtrlRegsP->GSR, // clearRegisterP
XS_AC97CTRL_GSR_SCRSM_SH ); // clearBitShift
// Bits1..3 of Slot 12
XsAc97CtrlSetStatusEntry (&XsAc97CtrlStatusTable [XS_AC97CTRL_STAT_SLT12_B1_3],
FALSE, // intIsSupported: No interrupt
NULL, // enableRegisterP: No interrupt
0, // enableBitShift: No interrupt
7u, // reportBitMaskGsr
XS_AC97CTRL_GSR_SCRSM_SH, // reportBitShiftGsr
NULL, // clearRegisterP: Can't clear
0 ); // clearBitShift: Can't clear
// Read Completion Status (error)
XsAc97CtrlSetStatusEntry (&XsAc97CtrlStatusTable [XS_AC97CTRL_STAT_RCS_ERR],
FALSE, // intIsSupported: No interrupt
NULL, // enableRegisterP: No interrupt
0, // enableBitShift: No interrupt
1u, // reportBitMaskGsr
XS_AC97CTRL_GSR_SCRSM_SH, // reportBitShiftGsr
&XsAc97CtrlRegsP->GSR, // clearRegisterP
XS_AC97CTRL_GSR_SCRSM_SH ); // clearBitShift
// Status Done
XsAc97CtrlSetStatusEntry (&XsAc97CtrlStatusTable [XS_AC97CTRL_STAT_SDONE],
FALSE, // intIsSupported
&XsAc97CtrlRegsP->GCR, // enableRegisterP
XS_AC97CTRL_GCR_SDONE_IE_SH, // enableBitShift
1u, // reportBitMaskGsr
XS_AC97CTRL_GSR_SDONE_SH, // reportBitShiftGsr
&XsAc97CtrlRegsP->GSR, // clearRegisterP
XS_AC97CTRL_GSR_SDONE_SH ); // clearBitShift
// Command Done
XsAc97CtrlSetStatusEntry (&XsAc97CtrlStatusTable [XS_AC97CTRL_STAT_CDONE],
FALSE, // intIsSupported
&XsAc97CtrlRegsP->GCR, // enableRegisterP
XS_AC97CTRL_GCR_CDONE_IE_SH, // enableBitShift
1u, // reportBitMaskGsr
XS_AC97CTRL_GSR_CDONE_SH, // reportBitShiftGsr
&XsAc97CtrlRegsP->GSR, // clearRegisterP
XS_AC97CTRL_GSR_CDONE_SH ); // clearBitShift
//
// End Initialize registered interrupt processing table
//
} // End XsAc97CtrlSWInit ()
/*
*******************************************************************************
*
* FUNCTION: XsAc97CtrlHWSetup
*
* DESCRIPTION: Register the AC'97 Controller interrupt handling
* subroutine with the Interrupt Controller driver module.
* Enable AC'97 Controller device clock.
* Perform a cold reset of the AC'97 controller and codec(s).
* Enable AC'97 Controller interrupts at the Int Controller.
* Note: Does not enable any interrupt types within the
* ACUNIT, so no interrupts should occur at this point.
*
* INPUT PARAMETERS: None
*
* RETURNS:
* Success: 0 (ERR_NONE)
* Failure: ERR_T_SW_INTERNAL: Internal SW error in this module or a
* subroutine. For details, examine the
* error history.
* ERR_T_NOBITSET: Clock manager failed to enable ACUNIT clock
* ERR_T_TIMEOUT: Took too long for at least one codec to
* respond as ready, after cold reset.
*
* GLOBAL EFFECTS: Error logged before return.
*
* ASSUMPTIONS: - No other systems, such as debuggers, are using the
* AC '97 Controller or codecs, or the AC Link.
* - The software system will be unharmed by a cold reset of
* the entire AC '97 subsystem and any associated devices.
*
* CALLS:
*
* CALLED BY:
*
* PROTOTYPE: UINT32 XsAc97CtrlHWSetup (void);
*
*******************************************************************************
*/
ErrorT XsAc97CtrlHWSetup (void)
{
ErrorT retVal = ERR_NONE;
// Force disable of ACUNIT interrupt, and force no handler installed.
// Assume valid IC signal ID for now.
(void) XsIcUnRegisterHandler (XSIC_AC97_SGNL);
// Also range-checks XSIC_AC97_SGNL
// retVal = XsIcRegisterHandler (XSIC_AC97_SGNL,
// XsAc97CtrlInterruptHandler,
// (void *) &XsAc97CtrlContext);
if (retVal == ERR_NONE)
{
// Enable clocking of AC '97 controller device in processor
retVal = xsCMEnableClock (AC97_CE);
}
if (retVal == ERR_NONE)
{
// Perform the cold reset.
// Also enables the codec(s), control unit and the control unit's FIFOs
retVal = XsAc97CtrlColdReset ();
// Note: this system has only one codec. For systems with a primary and
// secondary device, the identity of a device that did not properly
// reset could be ascertained at this point.
}
if (retVal != ERR_NONE)
{
// if ((ERR_T_NOBITSET != retVal) && (ERR_T_TIMEOUT != retVal))
// {
// // Other errors indicate a bad parameter, failure to clear any
// // existing handler by the interrupt controller driver, or
// // violation of the assumption that the AC'97 is unused by a
// // debugger. All are essentially software errors.
// // The error log, as filled in by the subroutines, should leave a
// // trace of exactly what the problem was.
//
// retVal = ERR_T_SW_INTERNAL;
// }
// LOGERROR (XsAc97CtrlContext.loggedError, ERR_L_XSAC97CTRL,
// ERR_S_XSAC97CTRL_HWSETUP, retVal, 0, 0, 0)
}
else
{
// No problems. Enable the AC'97 interrupts at the Int Controller
// Ignore return value, the parameter was range-checked above.
(void) XsIcEnableIrqDeviceInt (XSIC_AC97_SGNL);
}
return (retVal);
} // End XsAc97CtrlHWSetup ()
/*
*******************************************************************************
*
* FUNCTION: XsAc97CtrlRegisterHandler
*
* DESCRIPTION: Register an interrupt handling subroutine to be called
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