xsmemctrl.h

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/******************************************************************************
**
**  COPYRIGHT (C) 2000, 2001 Intel Corporation.
**
**  This software as well as the software described in it is furnished under
**  license and may only be used or copied in accordance with the terms of the
**  license. The information in this file is furnished for informational use
**  only, is subject to change without notice, and should not be construed as
**  a commitment by Intel Corporation. Intel Corporation assumes no
**  responsibility or liability for any errors or inaccuracies that may appear
**  in this document or any software that may be provided in association with
**  this document.
**  Except as permitted by such license, no part of this document may be
**  reproduced, stored in a retrieval system, or transmitted in any form or by
**  any means without the express written consent of Intel Corporation.
**
**  FILENAME:       xsmemctrl.h
**
**  PURPOSE:        This header file contains the definitions for the Intel(r)
**                  XScale(tm) Microarchitecture memory controller.
**
**  LAST MODIFIED:  $Modtime: 7/17/03 1:01p $
******************************************************************************/
#ifndef _XsMemCtrl_h
#define _XsMemCtrl_h

// Bulverde Memory Controller Base Address
#define MEMORY_CONTROL_BASE 0x48000000

// Bulverde Memory Controller Register Definitions.
typedef struct Memory_Control_RegisterS {
    VUINT32 MDCNFG;       // SDRAM Configuration Register 0
    VUINT32 MDREFR;       // SDRAM Refresh Control Register
    VUINT32 MSC0;         // Static Memory Control Register 0
    VUINT32 MSC1;         // Static Memory Control Register 1
    VUINT32 MSC2;         // Static Memory Control Register 2
    VUINT32 MECR;         // Expansion Memory Bus Configuration Register
    VUINT32 SXLCR;        // LCR value written to SDRAM Timing Synchronous Flash
    VUINT32 SXCNFG;       // Synchronous Static Memory Control Register
    VUINT32 FLYCNFG;      // Fly by DMA DVAL assert deassert times
    VUINT32 SXMRS;        // MRS value to be written to Synchronous Flash
    VUINT32 MCMEM0;       // Card Interface Common Memory Space Socket 0
    VUINT32 MCMEM1;       // Card Interface Common Memory Space Socket 1
    VUINT32 MCATT0;       // Card Interface Attribute Space Socket 0
    VUINT32 MCATT1;       // Card Interface Attribute Space Socket 1
    VUINT32 MCIO0;        // Card Interface I/O Space Socket 0
    VUINT32 MCIO1;        // Card Interface I/O Space Socket 1
    VUINT32 MDMRS;        // MRS value to be written to SDRAM
    VUINT32 BOOT_DEF;     // Read-Only Boot Time Register
} Memory_Control_RegisterT;


/*
*******************************************************************************
*    MCMEM0 and MCMEM1 Register Bitmap settings.
*    Refer to the Bulverde EAS for details.
*******************************************************************************
*/
#define MCMEM0_MEM0_SET  (0x11U << 0)
#define MCMEM0_MEM0_ASST (0x07U << 7)
#define MCMEM0_MEM0_HOLD (0x07U << 14)

#define MCMEM1_MEM1_SET  (0x011U << 0)
#define MCMEM1_MEM1_ASST (0x07U << 7)
#define MCMEM1_MEM1_HOLD (0x07U << 14)

/*
*******************************************************************************
*    MCATT0 and MCATT1 Register Bitmap settings.
*    Refer to the Bulverde EAS for details.
*******************************************************************************
*/
#define MCATT0_ATT0_SET  (0x11U << 0)
#define MCATT0_ATT0_ASST (0x07U << 7)
#define MCATT0_ATT0_HOLD (0x07U << 14)

#define MCATT1_ATT1_SET  (0x11U << 0)
#define MCATT1_ATT1_ASST (0x07U << 7)
#define MCATT1_ATT1_HOLD (0x07U << 14)

/*
*******************************************************************************
*    MCIO0 and MCIO1 Register Bitmap settings.
*    Refer to the Bulverde EAS for details.
*******************************************************************************
*/
#define MCIO0_IO0_SET  (0x11U << 0)
#define MCIO0_IO0_ASST (0x07U << 7)
#define MCIO0_IO0_HOLD (0x07U << 14)

#define MCIO1_IO1_SET  (0x11U << 0)
#define MCIO1_IO1_ASST (0x07U << 7)
#define MCIO1_IO1_HOLD (0x07U << 14)

// Expansion Memory (PCMCIA and Compact Flash) Configuration Register bits.
#define MECR_NOS    (0x1U << 0)    // Card Interface Number of Sockets
#define MECR_CIT    (0x1U << 1)    // Card Interface Card Is There

#endif // _XsMemCtrl_h