📄 tvcode.asm
字号:
;**************************************************************************
;*
;* TVCODE.ASM
;*
;* Copyright (c) 1999 National Semiconductor Corporation.
;* All Rights Reserved.
;*
;* Function:
;* TV tuner functionality.
;*
;* $Revision:: 1 $
;*
;**************************************************************************
;.MODEL TINY
.486P
INCLUDE MACROS.INC
INCLUDE DEF.INC
_TEXT SEGMENT PUBLIC use16 'CODE'
; NOTE: Only one of the following should be set to non-zero.
CH7001 EQU 0
CH7002 EQU 0
CH7003 EQU 1
AITECH EQU 0
;**************************************************************************
;* CHRONTEL 7002 DEFINITIONS ;
;**************************************************************************
CH7002_CHIP_ADDRESS EQU 0EAh ; chip address for I2C bus
CH7002_DISPLAY_MODE EQU 000h ; display mode register
CH7002_LUMA_FILTER EQU 002h ; Y (luma) filter register
CH7002_LUMA_DEFAULT EQU 003h ; Y (luma) filter value
CH7002_SAMPLE_DELAY EQU 003h ; sampling delay register
CH7002_SAMPLE_DEFAULT EQU 009h ; sampling delay value
CH7002_BLACK_LEVEL EQU 004h ; black level register
CH7002_POSITION_CONTROL EQU 005h ; position control register
CH7002_POSITION_NONE EQU 00Fh ; no action
CH7002_POSITION_DOWN EQU 00Eh ; move position down
CH7002_POSITION_UP EQU 00Dh ; move position up
CH7002_POSITION_LEFT EQU 007h ; move position left
CH7002_POSITION_RIGHT EQU 00Bh ; move position right
CH7002_MISC_CONTROL EQU 008h ; miscellaneous control
CH7002_CONNECT_DETECT EQU 009h ; connection detect register
CH7002_SENSE_HIGH EQU 001h ; connection detect sense high
CH7002_SENSE_LOW EQU 000h ; connection detect sense low
CH7002_DETECT_NONE EQU 00Eh ; connection detect status
;**************************************************************************
;* chrontel 7003 registers
;**************************************************************************
CH7003_CHIP_ADDRESS EQU 0EAh ; chip address for I2C bus
CH7003_DMR EQU 00h ; Display mode selection
CH7003_DMR_512x384 EQU 00000000b ; 512x384
CH7003_DMR_720x400 EQU 00100000b ; 720x400
CH7003_DMR_640x400 EQU 01000000b ; 640x400
CH7003_DMR_640x480 EQU 01100000b ; 640x480
CH7003_DMR_800x600 EQU 10000000b ; 800x600
CH7003_DMR_PAL EQU 00000000b ; PAL
CH7003_DMR_NTSC EQU 00001000b ; NTSC
CH7003_DMR_PALM EQU 00010000b ; PAL-M
CH7003_DMR_NTSCJ EQU 00011000b ; NTSC-J
CH7003_DMR_SR_5_4 EQU 00000000b ; 4/5
CH7003_DMR_SR_1_1 EQU 00000001b ; 1/1
CH7003_DMR_SR_7_8 EQU 00000010b ; 7/8
CH7003_DMR_SR_5_6 EQU 00000011b ; 5/6
CH7003_DMR_SR_3_4 EQU 00000100b ; 3/4
CH7003_DMR_SR_7_10 EQU 00000101b ; 7/10
CH7003_MODE_13 EQU CH7003_DMR_640x480 or CH7003_DMR_PAL or CH7003_DMR_SR_5_4
CH7003_MODE_14 EQU CH7003_DMR_640x480 or CH7003_DMR_PAL or CH7003_DMR_SR_1_1
CH7003_MODE_15 EQU CH7003_DMR_640x480 or CH7003_DMR_PAL or CH7003_DMR_SR_5_6
CH7003_MODE_16 EQU CH7003_DMR_640x480 or CH7003_DMR_NTSC or CH7003_DMR_SR_1_1
CH7003_MODE_17 EQU CH7003_DMR_640x480 or CH7003_DMR_NTSC or CH7003_DMR_SR_7_8
CH7003_MODE_18 EQU CH7003_DMR_640x480 or CH7003_DMR_NTSC or CH7003_DMR_SR_5_6
CH7003_MODE_19 EQU CH7003_DMR_800x600 or CH7003_DMR_PAL or CH7003_DMR_SR_1_1
CH7003_MODE_20 EQU CH7003_DMR_800x600 or CH7003_DMR_PAL or CH7003_DMR_SR_5_6
CH7003_MODE_21 EQU CH7003_DMR_800x600 or CH7003_DMR_PAL or CH7003_DMR_SR_3_4
CH7003_MODE_22 EQU CH7003_DMR_800x600 or CH7003_DMR_NTSC or CH7003_DMR_SR_5_6
CH7003_MODE_23 EQU CH7003_DMR_800x600 or CH7003_DMR_NTSC or CH7003_DMR_SR_3_4
CH7003_MODE_24 EQU CH7003_DMR_800x600 or CH7003_DMR_NTSC or CH7003_DMR_SR_7_10
CH7003_FF EQU 01h ; Flicker filter
; 02 not used
CH7003_VBW EQU 03h ; lumina & chroma bandwidth
CH7003_IDF EQU 04h ; input data format
; 05 not used
CH7003_CM EQU 06h ; clock mode to be used
CH7003_CM_CFRB EQU 10000000b ; chroma carrier lock
CH7003_CM_MS EQU 01000000b ; 1=master/ =0slave
CH7003_CM_MCP EQU 00010000b ; clock edge 0=neg edge, 1=pos edge
CH7003_SAV EQU 07h ; active video delay setting
CH7003_PO EQU 08h ; msb of position values
CH7003_PO_VP80_ EQU 00000001b ; vertical pos bit 8
CH7003_PO_HP80_ EQU 00000010b ; horizontal pos bit 8
CH7003_PO_SAV_8 EQU 00000100b ; start active video bit 9
CH7003_BLR EQU 09h ; black level adjustment
CH7003_HPR EQU 0ah ; Horizontal position
CH7003_VPR EQU 0bh ; Vertical position
; 0c not used
CH7003_SPR EQU 0dh ; sync polarity
CH7003_SPR_HSP EQU 00000001b ; horz. sync 0=low 1=high
CH7003_SPR_VSP EQU 00000010b ; vert. sync 0=low 1=high
CH7003_SPR_SYO EQU 00000100b ; sync dir 0-inpout 1-output
CH7003_SPR_DES EQU 00001000b ; Detect embed sysnc 0-from direct 1-embedded
CH7003_PMR EQU 0eh ; power modes
CH7003_PMR_COMP_OFF EQU 000b ; composite off
CH7003_PMR_POWER_DOWN EQU 001b ; normal off
CH7003_PMR_S_VID_OFF EQU 010b ; s-video off
CH7003_PMR_ON EQU 011b ; full power on
CH7003_PMR_FULL_OFF EQU 100b ; full power off
; 0f not used
CH7003_CDR EQU 10h ; connection detect
CH7003_CE EQU 11h ; contrast enhancement
; 12 not used
CH7003_MNE EQU 13h ; msb bits for PLLM and PLLN
CH7003_PLLM EQU 14h ; PLL M value
CH7003_PLLN EQU 15h ; PLL N value
; 16 not used
CH7003_BCO EQU 17h ; buffered clock output pin 41
CH7003_FSCI7 EQU 18h ; FSCI bits 28-31
CH7003_FSCI6 EQU 19h ; FSCI bits 24-27
CH7003_FSCI5 EQU 1ah ; FSCI bits 20-23
CH7003_FSCI4 EQU 1bh ; FSCI bits 16-19
CH7003_FSCI3 EQU 1ch ; FSCI bits 12-15
CH7003_FSCI2 EQU 1dh ; FSCI bits 8-11
CH7003_FSCI1 EQU 1eh ; FSCI bits 4-7
CH7003_FSCI0 EQU 1fh ; FSCI bits 0-3
CH7003_PLLC EQU 20h ; PLL & memory
CH7003_CVIC EQU 21h ; Control of civ value
CH7003_CIV2 EQU 22h ; civ bits 16-23
CH7003_CIV1 EQU 23h ; civ bits 8-15
CH7003_CIV0 EQU 24h ; civ bits 0-7
CH7003_VID EQU 25h ; device version #
; 26-29 reservedfor testing
CH7003_AR EQU 2ah ; current register being accessed
;**************************************************************************
;* the following macro will build the fsci bit table
;* entries given the FSCI
;**************************************************************************
SET_FSCI macro fsci
DB CH7003_FSCI7, ((fsci and 0f0000000h) shr 28) and 0fh
DB CH7003_FSCI6, ((fsci and 0f000000h) shr 24) and 0fh
DB CH7003_FSCI5, ((fsci and 00f00000h) shr 20) and 0fh
DB CH7003_FSCI4, ((fsci and 000f0000h) shr 16) and 0fh
DB CH7003_FSCI3, ((fsci and 0000f000h) shr 12) and 0fh
DB CH7003_FSCI2, ((fsci and 00000f00h) shr 8) and 0fh
DB CH7003_FSCI1, ((fsci and 000000f0h) shr 4) and 0fh
DB CH7003_FSCI0, fsci and 0000000fh
endm
;**************************************************************************
;* this macro build the table entries for MNE,PLLM and PLLN
;* given the pllm and plln values
;**************************************************************************
SET_PLLMN macro pllm,plln
DB CH7003_MNE, ((pllm shr 8) and 01h) or ((plln shr 7) and 06h)
DB CH7003_PLLM, pllm and 0ffh
DB CH7003_PLLN, plln and 0ffh
endm
IF CH7003
;**************************************************************************
;* mode initialization tables
;**************************************************************************
; common to all modes
ch7003_tab_common:
DB CH7003_IDF,00h ; input data format
DB CH7003_CM,CH7003_CM_MS or CH7003_CM_MCP
DB CH7003_SPR,00h
DB -1,0
; PAL 640x480 over
ch7003_tab_mode13:
DB CH7003_DMR,CH7003_MODE_13
DB CH7003_SAV,200
DB CH7003_PO,00h
SET_PLLMN 15,22
SET_FSCI 805940387
DB -1,0
; PAL 640x480 under 1
ch7003_tab_mode14:
DB CH7003_DMR,CH7003_MODE_14
DB CH7003_SAV,96
DB CH7003_PO,00h
SET_PLLMN 6,11
SET_FSCI 644752310
DB -1,0
; PAL 640x480 under 2
ch7003_tab_mode15:
DB CH7003_DMR,CH7003_MODE_15
DB CH7003_SAV,200
DB CH7003_PO,00h
SET_PLLMN 5,11
SET_FSCI 537296621
DB -1,0
; ntsc 640x480 over
ch7003_tab_mode16:
DB CH7003_DMR,CH7003_MODE_16
DB CH7003_SAV,40
DB CH7003_PO,00h
SET_PLLMN 65,112
SET_FSCI 623093737
DB -1,0
; ntsc 640x480 under 1
ch7003_tab_mode17:
DB CH7003_DMR,CH7003_MODE_17
DB CH7003_SAV,144
DB CH7003_PO,00h
SET_PLLMN 65,128
SET_FSCI 545079193
DB -1,0
; ntsc 640x480 under 2
ch7003_tab_mode18:
DB CH7003_DMR,CH7003_MODE_18
DB CH7003_SAV,160
DB CH7003_PO,00h
SET_PLLMN 91,192
SET_FSCI 509051625
DB -1,0
; PAL 800x600 over
ch7003_tab_mode19:
DB CH7003_DMR,CH7003_MODE_19
DB CH7003_SAV,144
DB CH7003_PO,00h
SET_PLLMN 315,649
SET_FSCI 537296621
DB -1,0
; PAL 800x600 under 1
ch7003_tab_mode20:
DB CH7003_DMR,CH7003_MODE_20
DB CH7003_SAV,160
DB CH7003_PO,00h
SET_PLLMN 35,88
SET_FSCI 528898379
DB -1,0
; PAL 800x600 under 2
ch7003_tab_mode21:
DB CH7003_DMR,CH7003_MODE_21
DB CH7003_SAV,135
DB CH7003_PO,00h
SET_PLLMN 105,286
SET_FSCI 488155031
DB -1,0
; ntsc 800x600 over
ch7003_tab_mode22:
DB CH7003_DMR,CH7003_MODE_22
DB CH7003_SAV,223
DB CH7003_PO,00h
SET_PLLMN 35,96
SET_FSCI 521907575
DB -1,0
; ntsc 800x600 under 1
ch7003_tab_mode23:
DB CH7003_DMR,CH7003_MODE_23
DB CH7003_SAV,223
DB CH7003_PO,00h
SET_PLLMN 64,21
SET_FSCI 469716817
DB -1,0
; ntsc 800x600 under 2
ch7003_tab_mode24:
DB CH7003_DMR,CH7003_MODE_24
DB CH7003_IDF,00h
DB CH7003_SAV,247
SET_PLLMN 91,304
SET_FSCI 438327006
DB -1,0
ch7003_ntsc_modes:
DW OFFSET ch7003_tab_mode16 ; 640x480 over
DW OFFSET ch7003_tab_mode17 ; 640x480 under 1
DW OFFSET ch7003_tab_mode22 ; 800x600 over
DW OFFSET ch7003_tab_mode23 ; 800x600 under 1
ch7003_pal_modes:
DW OFFSET ch7003_tab_mode13 ; 640x480 over
DW OFFSET ch7003_tab_mode14 ; 640x480 under 1
DW OFFSET ch7003_tab_mode19 ; 800x600 over
DW OFFSET ch7003_tab_mode20 ; 800x600 under 1
ENDIF ; CH7003
SELECT_DDC EQU 80h
SELECT_I2C EQU 00h
EXTRN geodeI2cDdc:NEAR
PUBLIC Geode_Video_Interface
;**************************************************************************
;*
;* Geode_Video_Interface
;*
;* Entry:
;* Exit:
;* Destroys:
;*
;**************************************************************************
Geode_Video_Interface PROC NEAR
cmp ch, MAX_FUNC
jae SHORT Bad_Function
mov bl, ch
xor bh, bh
add bx, bx
jmp WORD PTR cs:[TV_Routines + bx]
Geode_Video_Interface ENDP
;**************************************************************************
;* Bad_Function
;*
;**************************************************************************
Bad_Function:
stc
ret
TV_Routines:
DW OFFSET Query_TV_Encoder ; CH = 0
DW OFFSET Set_TV_Mode ; CH = 1
DW OFFSET Adjust_TV_Position ; CH = 2
DW OFFSET Adjust_TV_Brightness ; CH = 3
DW OFFSET Adjust_TV_Output ; CH = 4
DW OFFSET Reset_Encoder ; CH = 5
DW OFFSET Bad_Function ; CH = 6
DW OFFSET Bad_Function ; CH = 7
DW OFFSET Bad_Function ; CH = 8
DW OFFSET Bad_Function ; CH = 9
DW OFFSET Bad_Function ; CH = A
DW OFFSET Bad_Function ; CH = B
DW OFFSET Bad_Function ; CH = C
DW OFFSET Bad_Function ; CH = D
DW OFFSET Bad_Function ; CH = E
DW OFFSET Bad_Function ; CH = F
DW OFFSET Return_DDC2_Status ; CH = 10h
DW OFFSET Return_DDC2_Information ; CH = 11h
MAX_FUNC EQU ($-TV_Routines)/2
;**************************************************************************
;*
;* TV_Init
;*
;* Configure TVOUT by CMOS setting
;* Set TV output mode
;* Set TV positions
;* Set TV format and resolution (the resolution is 640x480)
;*
;* Entry:
;* None
;*
;* Exit:
;* None
;*
;* Destroys:
;*;* Processing:
;*
;**************************************************************************
TV_Init PROC NEAR
ret
TV_Init ENDP
;**************************************************************************
;*
;* Query_TV_Encoder
;*
;* Entry:
;* CH = 00
;*
;* Exit:
;* DX = Encoder Type
;* 0000h - NONE
;* 0001h - AIT1108
;* 0002h - CH7002
;* 0100h - CH7001
;*
;* Destroys:
;*
;**************************************************************************
; public Query_TV_Encoder
Query_TV_Encoder PROC NEAR
IF CH7002
; Test if a CH7002 chip is populated by RMW on the black level register
mov bl, CH7002_CHIP_ADDRESS
mov cl, CH7002_BLACK_LEVEL
call OEMGetI2CRegister
cmp bl, 51 ; Is it a valid setting ?
jb SHORT No_TV_chip
cmp bl, 127
ja SHORT No_TV_chip
mov dl, bl
xor dl, 55h
and dl, 7Fh
mov bh, dl
push bx ; Save original value
mov bl, CH7002_CHIP_ADDRESS
mov cl, CH7002_BLACK_LEVEL
call OEMSetI2CRegister
mov bl, CH7002_CHIP_ADDRESS
mov cl, CH7002_BLACK_LEVEL
call OEMGetI2CRegister
pop ax
cmp bl, ah ; Were we able to RW the register ?
jne SHORT No_TV_chip
mov dl, al ; Yes, restore original black level value
mov bl, CH7002_CHIP_ADDRESS
mov cl, CH7002_BLACK_LEVEL
call OEMSetI2CRegister
mov dx, 0002h ; Signify that a CH7002 is present
elseif CH7003
; Test if a CH7003 chip is populated by RMW on the black level register
mov bl, CH7003_CHIP_ADDRESS
mov cl, CH7003_BLR
call OEMGetI2CRegister
cmp bl, 51 ; Is it a valid setting ?
jb SHORT No_TV_chip
cmp bl, 208
ja SHORT No_TV_chip
mov dl, bl
xor dl, 55h
and dl, 7Fh
mov bh, dl
push bx ; Save original value
mov bl, CH7003_CHIP_ADDRESS
mov cl, CH7003_BLR
call OEMSetI2CRegister
mov bl, CH7003_CHIP_ADDRESS
mov cl, CH7003_BLR
call OEMGetI2CRegister
pop ax
cmp bl, ah ; Were we able to RW the register ?
jne SHORT No_TV_chip
mov dl, al ; Yes, restore the original black level value
mov bl, CH7003_CHIP_ADDRESS
mov cl, CH7003_BLR
call OEMSetI2CRegister
; TEMP say 7002!!!!!!!!!!
mov dx, 0002h ; Signify that a CH7002 is present
elseif CH7001
mov dx, 0100h ; Signify that a CH7001 is present
elseif AIT1108
mov dx, 0001h ; Signify that a AIT1108 is present
ELSE
mov dx, 0000h ; Signify that no TV encoder is present
ENDIF
ret
No_TV_chip:
mov dx, 0000h ; Signify that no TV encoder is present
ret
Query_TV_Encoder ENDP
;**************************************************************************
;*
;* Set_TV_Mode
;*
;* Entry:
;* CH = 01
;*
;* Exit:
;* DL: bit 0 - selects underscan (otherwise overscan)
;* bit 1 - selects 800x600 (otherwise 640x480)
;* bit 7 - selects PAL (otherwise NTSC)
;*
;* Destroys:
;*
;**************************************************************************
Set_TV_Mode PROC NEAR
IF CH7002
lea di, NTSC_Timings
.IF (dl & 80h)
lea di, PAL_Timings
.ENDIF
mov bl, dl
and bx, 0003h
neg bx ; Make offset negative
mov dl, BYTE PTR cs:[di+bx-1] ; Get mode for TV encoder
neg bx
push dx ; save current mode
; 800x600 overscan is not a valid mode, so change CH = x3 to 02
.IF (bl == 3)
dec bl
.ENDIF
; Generate offset into timing table
mov al, SIZE VIDEO_TIMINGS
mul bl
add di, ax
push cs
pop es
mov ax, 4F14h ; Set timings
mov bx, 0103h
int 10h
; LOAD THE DISPLAY MODE
pop dx
push dx
call LoadDisplayMode
; RESET POSITIONING
; The Chrontel part uses a "relative" method of setting the position .
; Toggle a bit and it moves 4 pixels in that direction. Therefore,
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -