v1lcdtbl.asm

X86 GX1 BOOTLOAD代码 ,支持WINCE操作系统!

;**************************************************************************
;*
;*  V1lcdtbl.ASM
;*
;*  Copyright (c) 1998-1999 National Semiconductor Corporation.
;*  All Rights Reserved.
;*
;*  Function:
;*    LCD initialization table for VSA1.
;*
;*
;**************************************************************************

_TEXT SEGMENT PUBLIC use16 'CODE'

;
; 640x480 TFT
;
PUBLIC LCD_INIT_TABLE0
PUBLIC LCD_INIT_COUNT0
LCD_INIT_TABLE0:
	DB	030h, 000h
	DB	030h, 057h	; 
	DB	030h, 04Ch	; Access Extended Registers Enable

	DB	50h , 00h	; Disable CRT and LCD before Init

	DB	51h , 01h	; Hitachi Flat Panel, Flat Panel is Present
	DB	52h , 10h	; 18Bits Per Pixel, 640x480
	DB	53h , 31h	; Two Pix per clock, 1 Power Sequence Delay
	DB	54h , 00h	; No Dither, No Frame Rate Modulation
	DB	55h , 32h	; Clock Frequency
	DB	56h , 14h	; Horizontal Total
	DB	57h , 2Dh	; Veritcal Total
	DB	58h , 02h	; Horizontal Sync Start
	DB	59h , 0Eh	; Horizontal Sync End
	DB	5ah , 09h	; Veritcal Sync Start
	DB	5bh , 0bh	; Veritcal Sync End
	DB	5ch , 02h	; CRT Horizontal Sync Start
	DB	5dh , 0Eh	; CRT Horizontal Sync End
	DB	5eh , 0Ah	; CRT Veritcal Sync Start
	DB	5fh , 0Ch	; CRT Veritcal Sync End
	
	DB	50h , 03h	; Enabled LCD AND CRT
	DB	030h, 0ffh	; Disable Access to extended registers
LCD_INIT_COUNT0 EQU ($ - LCD_INIT_TABLE0)

;
; 800x600 TFT
;
PUBLIC LCD_INIT_TABLE1
PUBLIC LCD_INIT_COUNT1
LCD_INIT_TABLE1:
	DB	030h, 000h	
	DB	030h, 057h	; 
	DB	030h, 04Ch	; Access Extended Registers Enable

	DB	50h , 00h	; Disable CRT and LCD before Init

	DB	51h , 11h	; Hitachi Flat Panel, Flat Panel is Present
	DB	52h , 21h	; 18Bits Per Pixel, 800x600
	DB	53h , 31h	; Two Pix per clock, 1 Power Sequence Delay
	DB	54h , 00h	; No Dither, No Frame Rate Modulation
	DB	55h , 50h	; Clock Frequency
	DB	56h , 20h	; Horizontal Total
	DB	57h , 1ch	; Veritcal Total
	DB	58h , 05h	; Horizontal Sync Start
	DB	59h , 15h	; Horizontal Sync End
	DB	5ah , 00h	; Veritcal Sync Start
	DB	5bh , 04h	; Veritcal Sync End
	DB	5ch , 05h	; CRT Horizontal Sync Start
	DB	5dh , 15h	; CRT Horizontal Sync End
	DB	5eh , 0bh	; CRT Veritcal Sync Start
	DB	5fh , 0fh	; CRT Veritcal Sync End
	
	DB	50h , 03h	; Enabled LCD AND CRT
	DB	030h, 0ffh	; Disable Access to extended registers
LCD_INIT_COUNT1 EQU ($ - LCD_INIT_TABLE1)

;
; 1024x768 TFT
;
PUBLIC LCD_INIT_TABLE2
PUBLIC LCD_INIT_COUNT2
LCD_INIT_TABLE2:
	DB	030h, 000h
	DB	030h, 057h	; 
	DB	030h, 04Ch	; Access Extended Registers Enable
	DB	50h , 00h	; Disable CRT and LCD before Init

	DB	51h , 01h	; Hitachi Flat Panel, Flat Panel is Present
	DB	52h , 12h	; 18Bits Per Pixel, 1024x768
	DB	53h , 31h	; Two Pix per clock, 1 Power Sequence Delay
	DB	54h , 00h	; No Dither, No Frame Rate Modulation
	DB	55h , 50h	; Clock Frequency
	DB	56h , 28h	; Horizontal Total
	DB	57h , 20h	; Veritcal Total
	DB	58h , 0ch	; Horizontal Sync Start
	DB	59h , 1ch	; Horizontal Sync End
	DB	5ah , 0dh	; Veritcal Sync Start
	DB	5bh , 13h	; Veritcal Sync End
	DB	5ch , 05h	; CRT Horizontal Sync Start
	DB	5dh , 15h	; CRT Horizontal Sync End
	DB	5eh , 0bh	; CRT Veritcal Sync Start
	DB	5fh , 0fh	; CRT Veritcal Sync End

	DB	50h , 03h	; Enabled LCD AND CRT
	DB	030h, 0ffh	; Disable Access to extended registers
LCD_INIT_COUNT2 EQU ($ - LCD_INIT_TABLE2)

;
; Unfixed timings
;
PUBLIC LCD_INIT_TABLE3
PUBLIC LCD_INIT_COUNT3
LCD_INIT_TABLE3:
	DB	030h, 000h
	DB	030h, 057h	; 
	DB	030h, 04Ch	; Access Extended Registers Enable
	DB	50h , 02h	; Disable CRT and LCD before Init
	DB	030h, 0ffh	; Disable Access to extended registers

LCD_INIT_COUNT3 EQU ($ - LCD_INIT_TABLE3)



_TEXT ENDS

END