bldt.asm

X86 GX1 BOOTLOAD代码 ,支持WINCE操作系统!

;**************************************************************************
;*                                                                        *
;*  BLDT.ASM                                                              *
;*                                                                        *
;*  Copyright (c) 1999 National Semiconductor Corporation.                *
;*  All Rights Reserved.                                                  *
;*                                                                        *
;*  $Revision:: 5                                                         $
;*  Note: Set Tabs to 8 spaces for proper viewing of this file            *
;**************************************************************************

 	.486P

	INCLUDE MACROS.INC	; Macros used throughout
	INCLUDE DEF.INC		; EQU Definitions
	INCLUDE PORT80.INC	; Post code Definitions
	INCLUDE 5530.INC
	INCLUDE STRINGS.INC



_TEXT SEGMENT PUBLIC use16 'CODE'

	ASSUME CS:SEGGROUP

	EXTERN	preSioInit:NEAR
	EXTERN	cpuRegInit:NEAR
	EXTERN	unreal:NEAR
	EXTERN	cpuMemRegInit:NEAR
	EXTERN	cpuTest:NEAR
	EXTERN	memSetup:NEAR
	EXTERN	memSetUpStack:NEAR
	EXTERN	memTest:NEAR
	EXTERN	memRAMoptimize:NEAR
	EXTERN	CacheInit:NEAR
	EXTERN	chipsetInit:NEAR
	EXTERN	sioTest:NEAR
	EXTERN	intTable:NEAR
	EXTERN	romCopy:NEAR
	EXTERN	cpuCacheOn:NEAR	
	EXTERN	cpuCacheOff:NEAR
	EXTERN	shadowRom:NEAR
	EXTERN	northBridgeInit:NEAR
	EXTERN	ResetLimits:NEAR
	EXTERN	pcATjunk:NEAR
	EXTERN	clockInit:NEAR
	EXTERN	optionRomInit:NEAR
	EXTERN	cpuLateInit:NEAR
	EXTERN	UserPreInit:NEAR
	EXTERN	UserRomInit:NEAR
	EXTERN	UserPostInit:NEAR
	EXTERN	UserCpuInitBX:NEAR
	EXTERN	UserChipsetInit:NEAR
	EXTERN	endPostSMI:NEAR
	EXTERN	setIBUs:NEAR
	EXTERN	pciScan:NEAR
        Extern  PCICfgRead32:NEAR
;
; Beginning of Test Code to Execute
;

	org	0000h

PUBLIC startTest
startTest::
	PORT80	POST_UserPreInit	; post_80h
	NOSTACK	bx, UserPreInit

	PORT80	POST_preSioInit		; post_00h
	NOSTACK	bx, preSioInit		; Set up any SIO specifics

	PORT80	POST_clockInit		; post_01h
	NOSTACK	bx, clockInit		; Init PLL's if any to init.

	PORT80	POST_CPURegInit		; post_02h
	NOSTACK	bx, cpuRegInit
	NOSTACK	bx, UserCpuInitBX

	PORT80	POST_UNREAL		; post_03h
	NOSTACK	dx, UNREAL		; Setup unReal mode

	PORT80	POST_CPUMemRegInit	; post_04h
	NOSTACK	bx, cpuMemRegInit	; Need to be in unReal

	PORT80	POST_CPUTest		; post_05h
	NOSTACK	bx, cpuTest		; GxmID

	PORT80	POST_memSetup		; post_06h
	NOSTACK bx, memSetup		; Initialize memory controller

	PORT80	POST_memSetUpStack	; post_07h
	NOSTACK	bx, memSetUpStack	; Setup a stack

	PORT80	POST_memTest		; post_08h
	NOSTACK	bx, memTest		; Test Memory Address Lines

	PORT80	POST_shadowRom		; post_09h
	NOSTACK bx, shadowRom		; Shadow the rom from F000:0 to F000:FFFF

	PORT80	POST_memRAMoptimize	; post_0ah
	NOSTACK	bx, memRAMoptimize	; SDRAM optimization. Use after validation

	PORT80	POST_cacheInit		; post_0bh
	call	CacheInit		; Cache Init.

	PORT80	POST_cpuLateInit	; post_13h
	call	cpuLateInit		; Load Late CPU Registers

	PORT80	POST_northBridgeInit	; post_0ch
	NOSTACK bx, northBridgeInit	; Load Cpu North Bridge

	PORT80	POST_chipsetInit	; post_0dh
	NOSTACK	bx, chipsetInit		; Load Cx55x0 with default/known values
	call	UserChipsetInit		; Platform specific chipset Init

	PORT80	POST_sioTest		; post_0eh
	NOSTACK	bx, sioTest		; SIO Test/Init

	PORT80	POST_pcATjunk		; post_0fh
	NOSTACK	bx, pcATjunk		; Init dma & timer 1

	PORT80	POST_intTable		; post_10h
	NOSTACK bx, intTable		; Set up generic interrupt Table

	PORT80	POST_pciScan		; post_17h
	call	pciScan

	PORT80	POST_romCopy		; post_12h
	NOSTACK	bx, romCopy		; VSA, Video, Keyboard, Int 13(HD's), Splash Screen

	PORT80	POST_Equipment_check	; post_82h
	call	setIBUs			; set internal registers to required vals
	
	PORT80	POST_optionRomInit	; post_18h
	call	UserRomInit		; Platform specific ROM pre-scan
	call	optionRomInit		; Scan and call options roms from C800-EFF0

	PORT80	POST_ResetLimits	; post_19h
	call	ResetLimits

	PORT80	POST_UserPostInit	; post_81h
	call	UserPostInit

	PORT80	POST_summary_screen	; post_1ah
	call	endPostSMI		; Start power managment, etc

	msg     'Super Express Loader V1.00'
	crlf				;new line
	msg	'Copyright 2003 SeaTech Computer Inc. '
	crlf
	msg	'Operating System is loading, please wait...'	
	PORT80	POST_Boot		; post_1bh
	int	19h			; Try int13 style boot
	int	18h			; Boot failed

	msg	'SeaTech Computer Inc. Super Express Loader Fail!'
	crlf

	PORT80	P80_PASSED		; Test Finished
Finished:
	cli
	hlt
	jmp	Finished

_TEXT ENDS

END