cache.asm

X86 GX1 BOOTLOAD代码 ,支持WINCE操作系统!

;**************************************************************************
;* 
;*  CACHE.ASM
;* 
;*  Copyright (c) 1999-2001 National Semiconductor Corporation. 
;*  All Rights Reserved. 
;* 
;*  Function: 
;*      Turn on L1 cache to write-back
;* 
;*  $Revision:: 2  $
;**************************************************************************

.486P

	INCLUDE MACROS.INC			; Macros
	INCLUDE DEF.INC				; Definitions
	INCLUDE PORT80.INC
	INCLUDE OPTIONS.INC

_TEXT SEGMENT PUBLIC use16 'CODE'

;**************************************************************************
;*
;*	cpuCacheOn 
;*
;*	Entry:
;*	Exit:
;*	Modified:
;*	Processing:
;*
;**************************************************************************
cpuCacheOn PROC NEAR PUBLIC
	
	mov	al, MDEBUG		; Is MTEST pins on?
	cmp	al, 1
	je	cacheStaysOff		; Dont turn on the cache, period.


	mov	al, CACHEON		; Is CACHEON set to off?
	cmp	al, 0
	je	cacheStaysOff		; Dont turn on the cache, period.



	mov	eax, cr0
	and	eax, 09FFFFFFFh			; Enable cache, write through
	mov	cr0, eax

	jmp $+2						; delay and dump prefetch queue
	wbinvd

	mov	eax, cr0
	or	eax, 020000000h			; Turn on write back
	mov	cr0, eax

cacheStaysOff:
;**************************************************************
; now we set the lock_nw bit
;**************************************************************
	mov 	al,CPU_CCR2		; set index to ccr2
	out	CPU_INDEX,al		; write index
	in	al,CPU_DATA		; read data
	or	al,00000100b		; set bit 2
	xchg	al,ah			; save in ah
	mov 	al,CPU_CCR2		; set index to ccr2
	out	CPU_INDEX,al		; write index
	xchg	al,ah
	out	CPU_DATA,al

	jmp	dx
cpuCacheOn ENDP

;**************************************************************************
;*
;*	cpuCacheOff
;*
;*	Entry:
;*	  BX - Return address
;*
;*	Exit:
;*	  BX - Return address
;*
;*	Modified:
;*	  EAX, EDI
;*	  All other registers preserved
;*
;*	Processing:
;*	  Disable Cpu cache.  (Stackless)
;*
;**************************************************************************
cpuCacheOff PROC NEAR PUBLIC
	mov	eax, cr0
	or	eax, 040000000h	; Disable cache, don't touch NW bit
	mov	cr0, eax

	jmp $+2				; delay and dump prefetch queue
	wbinvd				; Flush Cpu cache

	jmp	dx
cpuCacheOff	ENDP

;**************************************************************************
;*
;*	cacheInit
;*
;*	Entry:
;*	Exit:
;*	Modified:
;*	Processing:
;*
;**************************************************************************
cacheInit PROC NEAR PUBLIC

	mov	al, MDEBUG		; Is MTEST pins on?
	cmp	al, 1
	je	noCacheTest	; Dont turn on the cache, period.

	mov	al, CACHEON		; Is CACHEON set to off?
	cmp	al, 0
	je	noCacheTest	; Dont turn on the cache, period.

; MAPEN MUST BE ALREADY ENABLED 
; Disable scratch pad for cache test
;
	mov	al, CPU_GXI_GCR
	out	CPU_INDEX, al
	in	al, CPU_DATA
	mov	bl, al			;store gcr to use later
	mov	al, CPU_GXI_GCR
	out	CPU_INDEX, al
	mov	al, bl
	and	al, not 0ch
	out	CPU_DATA, al
;
; Enable memory window Read/Write/Cache 
;
	mov	esi, GX_BASE + CPU_BC_XMAP_3
	mov	eax, es:[esi]
	or	eax, 000007777h
	mov	es:[esi], eax
;
; Fillup with zeros for the correct test
;
	mov	edi, CACHE_TEST_ADDRESS
	mov	ecx, 4000h
	xor	eax, eax
	rep stosd es:[edi]
;
; Enable cache and fillup cache lines in a 64K area
; Cache lines must point into the last 16K area
;
	mov	eax, cr0
	and	eax, not 060000000h		; Enable cache, write through
	mov	cr0, eax
	or	eax, 040000000h			; Set disable cache bit for later
	mov	edx, eax
	mov	esi, CACHE_TEST_ADDRESS
	mov	ecx, 4000h
	rep lodsd es:[esi]
	mov	cr0, edx				; Disable cache
	jmp	$+2						; Delay and dump prefetch queue
;
; Disable memory window write
;
	mov	esi, GX_BASE + CPU_BC_XMAP_3
	mov	eax, es:[esi]
	and	eax, not 000006666h	; Cache off, write off
	mov	es:[esi], eax
;
; We can see writable when cache is loaded only
;
	mov	ecx, 8000h
	mov	eax, 69696969h
	call	testCache		; Test cache size with pattern 55AA55AAh
	cmp	cx, 4000h		; Compare is it 16K?
	jnz	cacheError

	mov	eax, 96969696h
	call	testCache  		; Test cache size with pattern AA55AA55h
	cmp	cx, 4000h		; Compare is it 16K?
	jz	cacheOk


cacheError:
	PORT80	POST_CacheInitError		;post_cfh
	hlt
cacheOk:
;
; Disable memory window
;
	mov	esi, GX_BASE + CPU_BC_XMAP_3
	mov	eax, es:[esi]
	and	eax, not 000007777h	; Memory area disabled
	mov	es:[esi], eax
;
; Enable scratch pad after the cache test
;
	mov	al, CPU_GXI_GCR
	out	CPU_INDEX, al
	mov	al, bl			;restore previous value
	out	CPU_DATA, al

noCacheTest:
;
; Init scratch Pad with Cyrix algorithm.  Always do this so video and audio work properly.
; This should be done after the cache has been tested, but if the cache shouldn't be 
; turned on, do it anyway.
;
	EXTERN	setVideoDramConfig:NEAR
	NOSTACK	bx, setVideoDramConfig	; Get scratch pad ready

;
; Enable the cache, maybe!  cpuCacheOn tests the state of the MTEST and
; CACHEON to determine whether the cache really gets turned on.  
;
	NOSTACK	dx, cpuCacheOn		; Turn the Cache ON
	
	ret
cacheInit ENDP

;**************************************************************************
;*
;*	testCache
;*
;*	Entry:
;*	Exit:
;*	Modified:
;*	Processing:
;*
;**************************************************************************
testCache PROC
	mov	edi, CACHE_TEST_ADDRESS + 10000h
	sub	edi, ecx
	shr	ecx, 2
	rep stosd es:[edi]

	mov	edi, CACHE_TEST_ADDRESS+0FFFCh
	xor	ecx, ecx
testNext:
	cmp	es:[edi], eax
	jnz	exit
	add	ecx,4
	sub	edi, 4
	cmp	edi, CACHE_TEST_ADDRESS
	jnc	testNext
exit:

	ret
testCache ENDP

_TEXT ENDS

END