📄 cx9211.asm
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;**************************************************************************
;* *
;* CX9211.ASM *
;* *
;* Copyright (c) 1998-1999 National Semiconductor Corporation. *
;* All Rights Reserved. *
;* *
;* Function: *
;* Initialization for the 9211 DSTN controller. *
;* *
;* $Revision:: 1 $
;**************************************************************************
.486P
INCLUDE MACROS.INC ; Macros used throughout
INCLUDE DEF.INC ; EQU Definitions
INCLUDE PORT80.INC ; Post code Definitions
INCLUDE STRINGS.INC ; New macros and defines
INCLUDE OPTIONS.INC
_TEXT SEGMENT PUBLIC use16 'CODE'
extern hex_dword:NEAR
extern Delay_100_mSec:NEAR
;;; Data Ports
CLOCKP9211 EQU 0E0h
DATAINP9211 EQU 0E4h
DATAOUTP9211 EQU 0E0h
CSP9211 EQU 0E4h
;;; Pin MASKS
CLOCK9211 EQU 010h
DATAIN9211 EQU 002h ;data going into the 9211
DATAOUT9211 EQU 080h ;data coming from the 9211
CS9211 EQU 001h
;**************************************************************************
;*
;* cx9211init
;*
;* Entry:
;* Exit:
;* Destroys:
;*
;**************************************************************************
cx92xxinit PROC NEAR PUBLIC
pusha
pushf
call Delay_100_mSec
call Delay_100_mSec
call cx9211gpioInit ; Get the GPIO's ready, direction & state.
; Wake up the Cx9211 Per Section 3.6 of 9211 data book
mov cx, 5
cld
clockInit9211:
call cx9211toggleClock
loop clockInit9211
mov cx, TableLength
lea si, TableStart
; turn off the flat panel
mov bx, 0480h
mov eax, 0h
call cx9211writeReg
call Delay_100_mSec ; spec says wait for 32ms*4
call Delay_100_mSec ; spec says wait for 32ms*4
DSTNLoop:
mov bx, cs:[si] ; Get index
add si, 2 ; Advance table pointer
mov eax, cs:[si] ; Get data
add si, 4
call cx9211writeReg
loop DSTNLoop
;Check for Rev C
mov bx, 0430h
call cx9211readReg
cmp eax, 92110201h ;RevC
jne noRevC
; load up the 32x64 FRM Memory
mov si, RevCFRMtable
xor dx, dx
mov cx, 64
writeFRM:
mov bx, 0418h
movzx eax, dx
call cx9211writeReg
mov bx, 041Ch
mov eax, cs:[si]
call cx9211writeReg
inc dx
add si, 4
loop writeFRM
; The first FRM location (64 bits) does not program correctly.
; This location always reads back with the last value programmed.
; ie. If 32 64-bit values are programmed, location 0 reads back as the 32nd
; If 30 locations are programmed, location 0 reads back as the 30th, etc.
; Fix this by re-writing location 0 after programming all 64 in the writeFRM loop in RevCFrmload() in CS9211.
mov bx, 0418h
xor eax, eax
call cx9211writeReg
mov bx, 041Ch
xor eax, eax
call cx9211writeReg
mov bx, 041Ch
xor eax, eax
call cx9211writeReg
; end fix
noRevC:
; turn on the flat panel
mov bx, 0480h
mov eax, 01000000h
call cx9211writeReg
call Delay_100_mSec ; spec says wait for 32ms*4
call Delay_100_mSec ; spec says wait for 32ms*4
popf
popa
ret
cx92xxinit ENDP
cx9211gpioInit PROC NEAR PUBLIC
push dx
push ax
; Set direction for all PINS used (This was probably set in SIO init but let's be sure.)
mov dx, CSP9211+1 ; 0E5h, Direction reg for P2
in al, dx
or al, CS9211 ; bit0 is CS, make output
and al, NOT DATAIN9211 ; bit1 is DO (from 9211), make input
out dx, al
mov dx, CLOCKP9211+1 ; 0E1h, Direction reg for P1
in al, dx
or al, CLOCK9211 ; bit4 is CLK, make output
or al, DATAOUT9211 ;bit7 is DI (to 9211), make output
out dx, al
; Set all PINS low
mov dx, CSP9211
in al, dx
and al, NOT CS9211
out dx, al
mov dx, CLOCKP9211
in al, dx
and al, NOT CLOCK9211
out dx, al
mov dx, DATAOUTP9211
in al, dx
and al, NOT DATAOUT9211
out dx, al
mov dx, DATAINP9211
in al, dx
and al, NOT DATAIN9211
out dx, al
pop ax
pop dx
ret
cx9211gpioInit ENDP
;------------------------------------------------
; Read an indexed register from Cx9211
;
; BX contains Register to Read
; EAX contains Data on Exit, BX is maintained.
cx9211readReg PROC NEAR PUBLIC
push ebx
push edx
push ecx
mov ax, bx ; Command in AX with INDEX
; Set CS
; Send Read
;
call cx9211clearDataout
call cx9211setDataOut
call cx9211setCS ; Set CS
call cx9211toggleClock ; 1 clock
call cx9211setDataOut
call cx9211toggleClock ; 1 clock
;
; Send Register INDEX to read
;
mov cx, 12 ; 12 bits to send
cld ; Count down
readRegIndexSend:
mov dl, al ; Put lower 8 bits into DL
and dl, 01h ; Mask off all but data bit
cmp dl, 1 ; Is it SET?
jne readRegIndexClr ; no Its CLEAR
readRegIndexSet:
call cx9211setDataOut
jmp readRegIndexClock
readRegIndexClr:
call cx9211clearDataOut
readRegIndexClock:
call cx9211toggleClock ; 1 clock
ror ax, 1 ; Move to Next Bit
loop readRegIndexSend
readRegIndexIdle:
call cx9211clearDataOut
call cx9211toggleClock ; 1 clock
; Idle Clock , 8 clocks, no data set.
call cx9211toggleClock ; 1 clock
call cx9211toggleClock ; 1 clock
call cx9211toggleClock ; 1 clock
call cx9211toggleClock ; 1 clock
call cx9211toggleClock ; 1 clock
call cx9211toggleClock ; 1 clock
call cx9211toggleClock ; 1 clock
call cx9211toggleClock ; 1 clock
xor edx, edx
mov cx, 31 ; 32 bits to read
cld ; Count down
readRegData:
call cx9211ReadDataIn ; read data
call cx9211toggleClock ; 1 clock
or dl, al ; store in dl
ror edx, 1 ; move data left one
loop readRegData
call cx9211ReadDataIn ; read data
call cx9211toggleClock ; 1 clock
or dl, al ; store in dl
ror edx, 1
call cx9211clearCS ; Clear CS
call cx9211toggleClock ; 1 clock
mov eax, edx ; eax contains value read
pop ecx
pop edx
pop ebx
ret
cx9211readReg ENDP
;------------------------------------------------
; write an indexed register from Cx9211
;
; BX contains Register to Read
; EAX contains Data
cx9211writeReg PROC NEAR PUBLIC
push ebx
push edx
push ecx
xchg ax, bx
; Set CS
; Send Write command
;
call cx9211clearDataout
call cx9211setDataOut
call cx9211setCS ; Set CS
call cx9211toggleClock ; 1 clock
call cx9211setDataOut
call cx9211toggleClock ; 1 clock
mov cx, 12 ; 12 bits to send
cld ; Count down
wrRegIndexSend:
mov dl, al ; Put lower 8 bits into DL
and dl, 01h ; Mask off all but data bit
cmp dl, 1 ; Is it SET?
jne wrRegIndexClr ; no Its CLEAR
wrRegIndexSet:
call cx9211setDataOut
jmp wrRegIndexClock
wrRegIndexClr:
call cx9211clearDataOut
wrRegIndexClock:
call cx9211toggleClock ; 1 clock
ror ax, 1
loop wrRegIndexSend
wrRegIndexIdle:
call cx9211setDataOut ; set write flag
call cx9211toggleClock ; 1 clock
; write data
xchg ax, bx
mov cx, 32 ; 8 bits to send
cld ; Count down
wrRegDataSend:
mov dl, al ; Put lower 8 bits into DL
and dl, 01h ; Mask off all but data bit
cmp dl, 1 ; Is it SET?
jne wrRegDataClr ; no Its CLEAR
wrRegDataSet:
call cx9211setDataOut
jmp wrRegDataClock
wrRegDataClr:
call cx9211clearDataOut
wrRegDataClock:
call cx9211toggleClock ; 1 clock
ror eax, 1
loop wrRegDataSend
call cx9211clearCS ; Set CS
call cx9211toggleClock ; 1 clock
call cx9211toggleClock ; 1 clock
call cx9211toggleClock ; 1 clock
call cx9211toggleClock ; 1 clock
pop ecx
pop edx
pop ebx
ret
cx9211writeReg ENDP
cx9211setCS PROC NEAR PUBLIC
pusha
; Set CS HIGH
mov dx, CSP9211
in al, dx
or al, CS9211
out dx, al
popa
ret
cx9211setCS ENDP
cx9211clearCS PROC NEAR PUBLIC
pusha
; Set CS LOW
mov dx, CSP9211
in al, dx
and al, NOT CS9211
out dx, al
popa
ret
cx9211clearCS ENDP
cx9211setDataOut PROC NEAR PUBLIC
pusha
; Set DATA HIGH
mov dx, DATAOUTP9211
in al, dx
or al, DATAOUT9211
out dx, al
popa
ret
cx9211setDataOut ENDP
cx9211clearDataOut PROC NEAR PUBLIC
pusha
; Set Data LOW
mov dx, DATAOUTP9211
in al, dx
and al, NOT DATAOUT9211
out dx, al
popa
ret
cx9211clearDataOut ENDP
cx9211readDataIn PROC NEAR PUBLIC
push DX
mov dx, DATAINP9211
in al, dx
in al, dx
in al, dx
in al, dx ; For sub-decode and settle time
and al, DATAIN9211 ; Preserve just Data IN bit
cmp al, 0 ; Is it LOW?
je readDataLow
mov al, 1 ; must be HIGH
readDataLow:
pop DX
ret
cx9211ReadDataIn ENDP
cx9211toggleClock PROC NEAR PUBLIC
pusha
; SET CLOCK
mov dx, CLOCKP9211
in al, dx
or al, CLOCK9211
out dx, al
; CLEAR CLOCK
mov dx, CLOCKP9211
in al, dx
and al, NOT CLOCK9211
out dx, al
popa
ret
cx9211toggleClock ENDP
cx9211SetClock PROC NEAR PUBLIC
pusha
; SET CLOCK
mov dx, CLOCKP9211
in al, dx
or al, CLOCK9211
out dx, al
popa
ret
cx9211SetClock ENDP
cx9211ClearClock PROC NEAR PUBLIC
pusha
; CLEAR CLOCK
mov dx, CLOCKP9211
in al, dx
and al, NOT CLOCK9211
out dx, al
popa
ret
cx9211ClearClock ENDP
TableStart LABEL BYTE
DSTNTable1: ;800x600, 16bpp, DSTN, Color
; Panel Timing Reg 1
dw 0400h
dd 02580000h
; Panel Timing Reg 2
dw 0404h
dd 00014000h
; Dither and Frame Rate Cntrl
dw 040Ch
dd 00000039h
; Block Select 1
dw 0410h
dd 25cf3096h
; Block Select 2
dw 0414h
dd 0ad47b81eh
; Dispersion 1
dw 0418h
dd 81a5d470h
; Dispersion 2
dw 041Ch
dd 29cfb63eh
; Memory Control
dw 0420h
dd 00000007h
TableLength EQU (($ - TableStart) / 6)
RevCFRMtable:
dd 000000000h ;0
dd 000000000h ;1
dd 001000100h ;2
dd 001000100h ;3
dd 001010101h ;4
dd 001010101h ;5
dd 002081041h ;6
dd 002081041h ;7
dd 010111111h ;8
dd 011111101h ;9
dd 049249241h ;10
dd 012412492h ;11
dd 092244891h ;12
dd 092244891h ;13
dd 022252525h ;14
dd 022252525h ;15
dd 0528294a5h ;16
dd 02528494ah ;17
dd 0294a5295h ;18
dd 0294a5295h ;19
dd 054a54a95h ;20
dd 02952a52ah ;21
dd 02a552a55h ;22
dd 02a552a55h ;23
dd 0554aa955h ;24
dd 02a9552aah ;25
dd 02aaa5555h ;26
dd 02aaa5555h ;27
dd 055555555h ;28
dd 02aaaaaaah ;29
dd 055555555h ;30
dd 055555555h ;31
dd 0aaaaaaabh ;32
dd 055555555h ;33
dd 05555aaabh ;34
dd 05555aaabh ;35
dd 0aab556abh ;36
dd 0556aad55h ;37
dd 055ab55abh ;38
dd 055ab55abh ;39
dd 0ab5ab56bh ;40
dd 056ad5ad5h ;41
dd 056b5ad6bh ;42
dd 056b5ad6bh ;43
dd 0ad6d6b5bh ;44
dd 05ad6b6b6h ;45
dd 05b5b5b5bh ;46
dd 05b5b5b5bh ;47
dd 05F6db6dbh ;48
dd 05F6db6dbh ;49
dd 0F776F776h ;50
dd 0F776F776h ;51
dd 0FBDEFBDEh ;52
dd 0FBDEFBDEh ;53
dd 07eFFBFF7h ;54
dd 07eFFBFF7h ;55
dd 0FF7FF7F7h ;56
dd 0FF7FF7F7h ;57
dd 0FF7FFF7Fh ;58
dd 0FF7FFF7Fh ;59
dd 0FFF7FFFFh ;60
dd 0FFF7FFFFh ;61
dd 0FFFFFFFFh ;62
dd 0FFFFFFFFh ;63
_TEXT ENDS
END
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