📄 memtimes.inc
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;***** Copyright (c) 2000 National Semiconductor Corporation ********
;****** All Rights Reserved. ****************************************
;
; File: memtimes.inc
;
; Summary: memory timings for GxM
;
; Contents:
;
; Author: Staff
;
; Last Edit: 11/09/2000 08:41:48 by Staff
;
; Notes:
;
; Revisions:
;
;********************************************************************
;********************************************************************
; check to see if equates have been done in bdcfg.inc
; if not then set the standard defaults
;********************************************************************
IFNDEF NUMBER_DIMMS
NUMBER_DIMMS EQU 2
ENDIF
IFNDEF DIMMADDRESS1
DIMMADDRESS1 equ 04h
ENDIF
IFNDEF DIMMADDRESS2
DIMMADDRESS2 equ 00h
ENDIF
;
; Number of DIMM sockets on the board
;
NumDimmModules DB NUMBER_DIMMS
;
; Address of the EEPROM in the DIMM Socket
; This will be how A0, A1, A2 are tied
; There must be the same number of entries as NUM_DIMM_MODULES
; DIMM0, DIMM1
;
DimmEEPROMAddr DB DIMMADDRESS1, DIMMADDRESS2
;
; Field that needs to be set to indicate if onboard SDRAM in addition to DIMMs
; IT IS ASSUMED THAT IF THIS IS SET THEN IT IS HOOKED UP LIKE IT IS A SINGLE
; DIMM BANK AND IF A DIMM IS PLACED INTO THE SOCKET THEN IT USES THE SAME
; CS#, RAS, CAS, BA, WE AND CAN ONLY BE A SINGLE DIMM BANK WITH THE SAME EXACT
; CONFIGURATION AS THE ON BOARD SDRAM. THE MEMORY CONTROLLER CAN ONLY DEAL
; WITH SYMMETRICAL DIMMS
; DIMM0, DIMM1
;
OnBoardSDRAM DB 00h, 00h
;
; These fields are the values for EEPROM
; Byte[ 3] #Row address lines
; Byte[ 4] #Column address lines
; Byte[ 5] #Dimm Banks
; Byte[17] #Banks/SDRAM
; Byte[31] Module Bank Density
; DIMM0, DIMM1
;
OnBoardSDRAMData DB 00h, 00h ; #row decoded
DB 00h, 00h ; #col decoded
DB 00h, 00h ; #DIMM Bank (HARDCODED TO 1 IN CODE)
DB 00h, 00h ; #Bank/SDRAM
DB 00h, 00h ; density 04H=16MB
;
; CAS Latency
;
OnBoardSDRAMCAS DB 00h, 00h ; CAS latency for onboard
;**************************************************************************
;
; SDRAM Timing Table
;
SDRAMTimingTable:
dw 0 ; Cpu speed < 100
dw 1 ; flags - OK CAS 2
dd SDCLK_SHIFT_SET1 OR 1 ; CPU_MC_MEM_CTRL2
dd 0A733220h
dd SDCLK_RATIO_SET2 OR 1800h ; CPU_MC_MEM_CNTRL1
SDRAMTimingEntrySize EQU $-SDRAMTimingTable
dw 170 ; 166mhz
dw 1 ; flags - OK CAS 2
dd 019h
dd 06423125h
dd 0B68A270Ch
dw 185 ; Cpu speed = 180MHz
dw 1 ; flags - OK CAS 2
dd 019h ; CPU_MC_MEM_CTRL2
dd 05423125h
dd 0B68E2B0Ch ; CPU_MC_MEM_CNTRL1
dw 210 ; Cpu speed = 200MHz
dw 1 ; flags - OK CAS 2
dd 021h
dd 06423125h
dd 0B68E310Ch
dw 240 ; Cpu speed = 233MHz
dw 1 ; flags - OK CAS 2
dd 028h ; CPU_MC_MEM_CTRL2
dd 06423125h
dd 0B692390Ch ; CPU_MC_MEM_CNTRL1
dw 270 ; Cpu speed = 266MHz
dw 1 ; flags - OK CAS 2
dd 028h ; CPU_MC_MEM_CTRL2
dd 06423125h
dd 0B6963F0Ch ; CPU_MC_MEM_CNTRL1
dw 310 ; 300mhz
dw 1 ; flags - OK CAS 2
dd 030h
dd 06423125h
dd 0B69A470Ch
dw 325 ; 315 mhz
dw 1 ; flags - OK CAS 2
dd 030h ; mc2
dd 06423125h ; sync
dd 0B69E4A0Ch ; mc1
dw 0ffffh ; >333 mhz
dw 1 ; flags - OK CAS 2
dd 030h ; mc2
dd 06423125h ; sync
dd 0B69E4F0Ch ; mc1
SDRAMTimingTableSize EQU $-SDRAMTimingTable
;**************************************************************************
;
; SDRAM Timing Table Gx1 PC66
;
SDRAMTimingTablePC66GX81:
dw 0 ; Cpu speed < 100
dw 1 ; flags - OK CAS 2
dd SDCLK_SHIFT_SET1 OR 1 ; CPU_MC_MEM_CTRL2
dd 0A733220h
dd SDCLK_RATIO_SET2 OR 1800h ; CPU_MC_MEM_CNTRL1
dw 170 ; 166mhz
dw 1 ; flags - OK CAS 2
dd 01Ah
dd 06423125h
dd 0B68A270Ch
dw 210 ; Cpu speed = 200MHz
dw 1 ; flags - OK CAS 2
dd 018h
dd 06423125h
dd 0B68E310Ch
dw 240 ; Cpu speed = 233MHz
dw 1 ; flags - OK CAS 2
dd 01Ah ; CPU_MC_MEM_CTRL2
dd 06423125h
dd 0B692390Ch ; CPU_MC_MEM_CNTRL1
dw 270 ; Cpu speed = 266MHz
dw 1 ; flags - OK CAS 2
dd 01Ah ; CPU_MC_MEM_CTRL2
dd 06423125h
dd 0B6963F0Ch ; CPU_MC_MEM_CNTRL1
dw 310 ; 300mhz
dw 1 ; flags - OK CAS 2
dd 022h
dd 06423125h
dd 0B69A470Ch
dw 0ffffh ; >333 mhz
dw 1 ; flags - OK CAS 2
dd 022h ; mc2
dd 06422125h ; sync
dd 0B69E4F0Ch ; mc1
;***************************************************************************************************
;
; PC100 Table for GX 5.4 and below
;
;***************************************************************************************************
SDRAMTimingTablePC100GX54:
dw 0 ; Cpu speed < 100
dw 1 ; flags - OK CAS 2
dd SDCLK_SHIFT_SET1 OR 1 ; CPU_MC_MEM_CTRL2
dd 0A733220h
dd SDCLK_RATIO_SET2 OR 1800h ; CPU_MC_MEM_CNTRL1
SDRAMTimingEntrySizePC100GX54 EQU $-SDRAMTimingTablePC100GX54
dw 170 ; 166mhz
dw 1 ; flags - OK CAS 2
dd 019h
dd 06423115h
dd 0B68A270Ch
dw 185 ; Cpu speed = 180MHz
dw 0 ; flags - no CAS 2
dd 019h
dd 07533115h
dd 0B68A2B0Ch
dw 210 ; Cpu speed = 200MHz
dw 1 ; flags - OK CAS 2
dd 021h
dd 06423125h
dd 0B68E310Ch
dw 250 ; Cpu speed = 233MHz
dw 0 ; flags - no CAS 2
dd 028h
dd 07533125h
dd 0B68E390Ch
dw 283 ; Cpu speed = 266MHz
dw 0 ; flags - no CAS 2
dd 028h
dd 07533125h
dd 0B6923F0Ch
dw 310 ; 300mhz
dw 0 ; flags - no CAS 2
dd 30h
dd 07533125h
dd 0B696470Ch
dw 325 ; 315 mhz
dw 0 ; flags - no CAS 2
dd 030h ; mc2
dd 06533125h ; sync
dd 0B69A4A0Ch ; mc1
dw 0ffffh ; >333 mhz
dw 0 ; flags - no CAS 2
dd 030h ; mc2
dd 07533125h ; sync
dd 0B69A4F0Ch ; mc1
SDRAMTimingTableSizePC100G54 EQU $-SDRAMTimingTablePC100GX54
;***************************************************************************************************
;
; PC100 Table for GX1 8.0 and up.
;
;***************************************************************************************************
SDRAMTimingTablePC100GX81:
dw 0 ; Cpu speed < 100
dw 1 ; flags - OK CAS 2
dd SDCLK_SHIFT_SET1 OR 1 ; CPU_MC_MEM_CTRL2
dd 0A733220h
dd SDCLK_RATIO_SET2 OR 1800h ; CPU_MC_MEM_CNTRL1
SDRAMTimingEntrySizePC100GX81 EQU $-SDRAMTimingTablePC100GX81
dw 170 ; 166mhz
dw 1 ; flags - OK CAS 2
dd 00Ah
dd 08533125h
dd 0B686270Ch
dw 185 ; Cpu speed = 180MHz
dw 0 ; flags - no CAS 2
dd 019h
dd 07533125h
dd 0B68A2B0Ch
dw 210 ; Cpu speed = 200MHz
dw 1 ; flags - OK CAS 2
dd 018h
dd 06423125h
dd 0B68E310Ch
dw 250 ; Cpu speed = 233MHz
dw 0 ; flags - no CAS 2
dd 018h
dd 07533125h
dd 0B68E390Ch
dw 283 ; Cpu speed = 266MHz
dw 0 ; flags - no CAS 2
dd 01Ah
dd 07533125h
dd 0B6923F0Ch
dw 310 ; 300mhz
dw 0 ; flags - no CAS 2
dd 01Ah
dd 07533125h
dd 0B696470Ch
dw 0ffffh ; >333 mhz
dw 0 ; flags - no CAS 2
dd 022h ; MC2
dd 07533125h ; sync
dd 0B69A4F0Ch ; MC1
SDRAMTimingTableSizePC100GX81 EQU $-SDRAMTimingTablePC100GX81
;***************************************************************************************************
;
; PC133 Table
;
;***************************************************************************************************
SDRAMTimingTablePC133:
dw 0 ; Cpu speed < 100
dw 1 ; flags - OK CAS 2
dd SDCLK_SHIFT_SET1 OR 1 ; CPU_MC_MEM_CTRL2
dd 0A733220h
dd SDCLK_RATIO_SET2 OR 1800h ; CPU_MC_MEM_CNTRL1
SDRAMTimingEntrySizePC133 EQU $-SDRAMTimingTablePC133
dw 170 ; 166mhz
dw 1 ; flags - OK CAS 2
dd 019h
dd 06423125h
dd 0B68A270Ch
dw 185 ; Cpu speed = 180MHz
dw 0 ; flags - no CAS 2
dd 012h
dd 08633125h
dd 0B6822B0Ch
dw 210 ; Cpu speed = 200MHz
dw 1 ; flags - OK CAS 2
dd 018h
dd 08633125h
dd 0B68E310Ch
dw 250 ; Cpu speed = 233MHz
dw 0 ; flags - no CAS 2
dd 012h
dd 08633125h
dd 0B68E3F0Ch
dw 283 ; Cpu speed = 266MHz
dw 0 ; flags - no CAS 2
dd 01Ah
dd 08633125h
dd 0B68E3F0Ch
dw 310 ; 300mhz
dw 0 ; flags - no CAS 2
dd 012h
dd 09633125h
dd 0B692470Ch
dw 0ffffh ; >333 mhz
dw 0 ; flags - no CAS 2
dd 012h ; mc2
dd 08633125h
dd 0B68E4F0Ch ; mc1
SDRAMTimingTableSizePC133 EQU $-SDRAMTimingTablePC133
;***************************************************************************************************
;
; Agressive PC100 Table for GX1 8.1 and up.
;
;***************************************************************************************************
AgressiveTimingTablePC100:
dw 210 ; Cpu speed = 200MHz
dw 1 ; flags - OK CAS 2
; div 2.5
dd 012h ; MC_MEM_CNTRL2
dd 005322115h ; MC_SYNC_TIM1
dd 0B68A310Ch ; MC_MEM_CNTRL1
AgressiveTimingEntrySizePC100 EQU $-AgressiveTimingTablePC100
dw 250 ; Cpu speed = 233MHz
dw 1 ; flags - CAS 2
; div 3.0
dd 018h ; MC_MEM_CNTRL2
dd 005322115h ; MC_SYNC_TIM1
dd 0B68E390Ch ; MC_MEM_CNTRL1
dw 283 ; Cpu speed = 266MHz
dw 1 ; flags - CAS 2
; div 3.0
dd 01Ah ; MC_MEM_CNTRL2
dd 006422115h ; MC_SYNC_TIM1
dd 0B68E3F0Ch ; MC_MEM_CNTRL1
dw 315 ; 300mhz
dw 1 ; flags - CAS 2
; div 3.5
dd 01Ah ; MC_MEM_CNTRL2
dd 005422115h ; MC_SYNC_TIM1
dd 0B692470Ch ; MC_MEM_CNTRL1
dw 0ffffh ; >315 mhz
dw 1 ; flags - CAS 2
; div 4.0
dd 01ah ; MC_MEM_CNTRL2
dd 005422115h ; MC_SYNC_TIM1
dd 0B6964F0Ch ; MC_MEM_CNTRL1
AgressiveTimingTableSizePC100 EQU $-AgressiveTimingTablePC100
;***************************************************************************************************
;
; Agressive PC133 Table
;
;***************************************************************************************************
AgressiveTimingTablePC133:
dw 210 ; Cpu speed = 200MHz
dw 1 ; flags - CAS 2
; div 2.0
dd 012h ; MC_MEM_CNTRL2
dd 006433115h ; MC_SYNC_TIM1
dd 0B686310Ch ; MC_MEM_CNTRL1
AgressiveTimingEntrySizePC133 EQU $-AgressiveTimingTablePC133
dw 250 ; Cpu speed = 233MHz
dw 1 ; flags - CAS 2
; div 2.0
dd 00ah ; MC_MEM_CNTRL2
dd 007533115h ; MC_SYNC_TIM1
dd 0B686390Ch ; MC_MEM_CNTRL1
dw 283 ; Cpu speed = 266MHz
dw 1 ; flags - CAS 2
; div 2.5
dd 012h ; MC_MEM_CNTRL2
dd 007433115h ; MC_SYNC_TIM1
dd 0B68A3F0Ch ; MC_MEM_CNTRL1
dw 315 ; 300mhz
dw 1 ; flags - CAS 2
; div 2.5
dd 012h ; MC_MEM_CNTRL2
dd 007533115h ; MC_SYNC_TIM1
dd 0B68A470Ch ; MC_MEM_CNTRL1
dw 0ffffh ; >315 mhz
dw 1 ; flags - CAS 2
; div 3.0
dd 012h ; MC_MEM_CNTRL2
dd 007433115h ; MC_SYNC_TIM1
dd 0B68E4F0Ch ; MC_MEM_CNTRL1
AgressiveTimingTableSizePC133 EQU $-AgressiveTimingTablePC133
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