📄 memtimes.inc
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;********************************************************************
; check to see if equates have been done in bdcfg.inc
; if not then set the standard defaults
;********************************************************************
IFNDEF NUMBER_DIMMS
NUMBER_DIMMS EQU 2
ENDIF
IFNDEF DIMMADDRESS1
DIMMADDRESS1 equ 00h
ENDIF
IFNDEF DIMMADDRESS2
DIMMADDRESS2 equ 00h
ENDIF
;
; Number of DIMM sockets on the board
;
NumDimmModules DB NUMBER_DIMMS
;
; Address of the EEPROM in the DIMM Socket
; This will be how A0, A1, A2 are tied
; There must be the same number of entries as NUM_DIMM_MODULES
; DIMM0, DIMM1
;
DimmEEPROMAddr DB DIMMADDRESS1, DIMMADDRESS2
;
; Field that needs to be set to indicate if onboard SDRAM in addition to DIMMs
; IT IS ASSUMED THAT IF THIS IS SET THEN IT IS HOOKED UP LIKE IT IS A SINGLE
; DIMM BANK AND IF A DIMM IS PLACED INTO THE SOCKET THEN IT USES THE SAME
; CS#, RAS, CAS, BA, WE AND CAN ONLY BE A SINGLE DIMM BANK WITH THE SAME EXACT
; CONFIGURATION AS THE ON BOARD SDRAM. THE MEMORY CONTROLLER CAN ONLY DEAL
; WITH SYMMETRICAL DIMMS
; DIMM0, DIMM1
;
OnBoardSDRAM DB 00h, 00h
;
; These fields are the values for EEPROM
; Byte[ 3] #Row address lines
; Byte[ 4] #Column address lines
; Byte[ 5] #Dimm Banks
; Byte[17] #Banks/SDRAM
; Byte[31] Module Bank Density
; DIMM0, DIMM1
;
OnBoardSDRAMData DB 00h, 00h ; #row decoded
DB 00h, 00h ; #col decoded
DB 00h, 00h ; #DIMM Bank (HARDCODED TO 1 IN CODE)
DB 00h, 00h ; #Bank/SDRAM
DB 00h, 00h ; density 04H=16MB
;
; CAS Latency
;
OnBoardSDRAMCAS DB 00h, 00h ; CAS latency for onboard
;***************************************************************************************************
;
; SDRAM Timing Table
;
; PC66 Table
;
;***************************************************************************************************
;
SDRAMTimingTable:
;166 MHz ; Assumes 33 MHz PCI Clock 5x Multiplier.
;DIV: 2.5 -> 66.4 MHz
dw 170 ; 166mhz
dw 1 ; flags - OK CAS 2
dd 000000018h ; CPU_MC_MEM_CTRL2
dd 06423125h ; MC_SYNC_TIM1
dd 0B68A2704h ; CPU_MC_MEM_CTRL1
SDRAMTimingEntrySize EQU $-SDRAMTimingTable
;200 MHz ; Assumes 33 MHz PCI Clock 6x Multiplier.
;DIV: 3.0 -> 66.7 MHz
dw 210 ; Cpu speed = 200MHz
dw 1 ; flags - OK CAS 2
dd 000000018h ; CPU_MC_MEM_CTRL2
dd 06423125h ; MC_SYNC_TIM1
dd 0B68E3104h ; CPU_MC_MEM_CTRL1
;233 MHz ; Assumes 33 MHz PCI Clock 7x Multiplier.
;DIV: 3.5 -> 66.6 MHz
dw 240 ; Cpu speed = 233MHz
dw 1 ; flags - OK CAS 2
dd 000000020h ; CPU_MC_MEM_CTRL2
dd 06423125h ; MC_SYNC_TIM1
dd 0B6923904h ; CPU_MC_MEM_CTRL1
;266 MHz ; Assumes 33 MHz PCI Clock 8x Multiplier.
;DIV: 4.0 -> 66.5 MHz
dw 270 ; Cpu speed = 266MHz
dw 1 ; flags - OK CAS 2
dd 000000020h ; CPU_MC_MEM_CTRL2
dd 06423125h ; MC_SYNC_TIM1
dd 0B6963F04h ; CPU_MC_MEM_CTRL1
;300 MHz ; Assumes 33 MHz PCI Clock 9x Multiplier.
;DIV: 4.5 -> 66.6 MHz
dw 0ffffh ; >270 mhz
dw 1 ; flags - OK CAS 2
dd 000000028h ; CPU_MC_MEM_CTRL2
dd 06423125h ; MC_SYNC_TIM1
dd 0B69A4704h ; CPU_MC_MEM_CTRL1
SDRAMTimingTableSize EQU $-SDRAMTimingTable
;***************************************************************************************************
;
; PC100 Table
;
;***************************************************************************************************
SDRAMTimingTablePC100:
;166 MHz ; Assumes 33 MHz PCI Clock 5x Multiplier.
;DIV: 2.5 -> 66.4 MHz
dw 170 ; 166mhz
dw 1 ; flags - OK CAS 2
dd 000000018h ; CPU_MC_MEM_CTRL2
dd 06423125h ; MC_SYNC_TIM1
dd 0B68A2704h ; CPU_MC_MEM_CTRL1
;200 MHz ; Assumes 33 MHz PCI Clock 6x Multiplier.
;DIV: 3.0 -> 66.7 MHz
dw 210 ; Cpu speed = 200MHz
dw 1 ; flags - OK CAS 2
dd 000000018h ; CPU_MC_MEM_CTRL2
dd 06423125h ; MC_SYNC_TIM1
dd 0B68E3104h ; CPU_MC_MEM_CTRL1
;233 MHz ; Assumes 33 MHz PCI Clock 7x Multiplier.
;DIV: 3.0 -> 77.7 MHz
dw 240 ; Cpu speed = 233MHz
dw 1 ; flags - OK CAS 2
dd 000000018h ; CPU_MC_MEM_CTRL2
dd 07533125h ; MC_SYNC_TIM1
dd 0B68E3904h ; CPU_MC_MEM_CTRL1
;266 MHz ; Assumes 33 MHz PCI Clock 8x Multiplier.
;DIV: 3.5 -> 76.0 MHz
dw 270 ; Cpu speed = 266MHz
dw 1 ; flags - OK CAS 2
dd 000000020h ; CPU_MC_MEM_CTRL2
dd 07533125h ; MC_SYNC_TIM1
dd 0B6923F04h ; CPU_MC_MEM_CTRL1
;300 MHz ; Assumes 33 MHz PCI Clock 9x Multiplier.
;DIV: 4 -> 75.0 MHz
dw 0ffffh ; >270 mhz
dw 1 ; flags - OK CAS 2
dd 000000020h ; CPU_MC_MEM_CTRL2
dd 07533125h ; MC_SYNC_TIM1
dd 0B6964704h ; CPU_MC_MEM_CTRL1
SDRAMTimingTableSizePC100 EQU $-SDRAMTimingTablePC100
;***************************************************************************************************
;
; PC133 Table
;
;***************************************************************************************************
SDRAMTimingTablePC133:
;166 MHz ; Assumes 33 MHz PCI Clock 5x Multiplier.
;DIV: 2.5 -> 66.4 MHz
dw 170 ; 166mhz
dw 3 ; flags - CAS 2 Forced
dd 000000018h ; CPU_MC_MEM_CTRL2
dd 06423125h ; MC_SYNC_TIM1
dd 0B68A2704h ; CPU_MC_MEM_CTRL1
;200 MHz ; Assumes 33 MHz PCI Clock 6x Multiplier.
;DIV: 3.0 -> 66.7 MHz
dw 210 ; Cpu speed = 200MHz
dw 3 ; flags - CAS 2 Forced
dd 000000018h ; CPU_MC_MEM_CTRL2
dd 06423125h ; MC_SYNC_TIM1
dd 0B68E3104h ; CPU_MC_MEM_CTRL1
;233 MHz ; Assumes 33 MHz PCI Clock 7x Multiplier.
;DIV: 3.0 -> 77.7 MHz
dw 240 ; Cpu speed = 233MHz
dw 1 ; flags - OK CAS 2
dd 000000018h ; CPU_MC_MEM_CTRL2
dd 07533125h ; MC_SYNC_TIM1
dd 0B68E3904h ; CPU_MC_MEM_CTRL1
;266 MHz ; Assumes 33 MHz PCI Clock 8x Multiplier.
;DIV: 3.0 -> 88.7 MHz
dw 270 ; Cpu speed = 266MHz
dw 1 ; flags - OK CAS 2
dd 000000018h ; CPU_MC_MEM_CTRL2
dd 07533125h ; MC_SYNC_TIM1
dd 0B68E3F04h ; CPU_MC_MEM_CTRL1
;300 MHz ; Assumes 33 MHz PCI Clock 9x Multiplier.
;DIV: 3 -> 100 MHz
dw 0ffffh ; >270 mhz
dw 1 ; flags - OK CAS 2
dd 000000018h ; CPU_MC_MEM_CTRL2
dd 08633125h ; MC_SYNC_TIM1
dd 0B68E4704h ; CPU_MC_MEM_CTRL1
SDRAMTimingTableSizePC133 EQU $-SDRAMTimingTablePC133
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