cpu.inc

X86 GX1 BOOTLOAD代码 ,支持WINCE操作系统!

;**************************************************************************
;*
;*  CPU.INC
;*
;*  Copyright (c) 1999-2000 National Semiconductor Corporation.
;*  All Rights Reserved.
;* 
;*  Function:
;*    GXm definitions.
;*
;**************************************************************************

;
; EQUATES
;
CHECKSUM_BYTE		EQU	64h
SIZE_SPDBUF		EQU	40h
TYPE_SDRAM		EQU	04h
RD_EEPROM_TRIES		EQU	02h
MAX_DIMM_BANKS		EQU	02h
MIN_DEV_BANKS		EQU	02h
MAX_DEV_BANKS		EQU	04h
MAX_COL_ADDR		EQU	0Bh
STDCLK_LOW		EQU	0FFFDFFFFh		; AND value to bring low
STDCLK_HIGH		EQU	000020000h		; OR value to bring high
REF_STAG_0		EQU	0FFFFFF3Fh		; AND value to set ref staggering
CLOCK_UNMASK		EQU	0FFFFF83Fh		; AND value to unmask clocks
PROGRAM_SDRAML		EQU	0FFFFFFFEh		; AND SDRAM program bit low
PROGRAM_SDRAMH		EQU	000002001h		; OR SDRAM program bit high
NUM_REFRESH_CYCLES	EQU	08h
REFRESH_L		EQU	0FFFFFFEFh		; AND to init refresh
REFRESH_H		EQU	000000010h		; OR to init refresh
UNMASK_CLK_DELAY	EQU	4h			; number of 120uS delays
NUM_REFRESH		EQU	8h			; number of ref to kick off
REFRESH_DELAY		EQU	4h			; number of 120uS delays

ENABLEDIMMWAIT1 equ 5000				; Number of IODELAYs
ENABLEDIMMWAIT2 equ 2000				; Number of IODELAYs

CPU_MC_MEM_CNTRL1_DEFAULT	EQU	024922440h	; default value for reg
CPU_MC_MEM_CNTRL2_MASK		EQU	0000007C0h	; or'd to mask SDCLK
CPU_MC_SYNC_TIM1_CASMASK	EQU	08FFFFFFFh	; and'd with CAS latency value
DIMM0_CLR_MASK			EQU	0FFFFA8FCh
DIMM1_CLR_MASK			EQU	0A8FCFFFFh

;
; Better equates
;
; CPU_MC_MEM_CNTLR1
PROGRAM_SDRAM_CLR	EQU	0FFFFFFFEh	; AND mask
PROGRAM_SDRAM_SET	EQU	 00000001h	; OR mask

VGA_WRAP_CLR		EQU	0FFFFFFFBh
VGA_WRAP_SET		EQU	1h SHL 2

XBUS_RR_CLR		EQU	0FFFFFFF7h
XBUS_RR_SET		EQU	1h SHL 3

TEST_REF_CLR		EQU	0FFFFFFEFh
TEST_REF_SET		EQU	1h SHL 4

TWO_CLK_SET		EQU	0FFFFFFDFh

REF_STAGGERING_CLR	EQU	0FFFFFF3Fh
REF_STAGGERING_SET1	EQU	1h SHL 6
REF_STAGGERING_SET2	EQU	2h SHL 6
REF_STAGGERING_SET4	EQU	3h SHL 6

REF_INTERVAL_CLR	EQU	0FFFE00FFh
; no sets for ref interval figure it out

SDCLK_START_CLR		EQU	0FFFDFFFFh
SDCLK_START_SET		EQU	1h SHL 17

SDCLK_RATIO_CLR		EQU	0FFE3FFFFh
SDCLK_RATIO_SET2	EQU	1h SHL 18
SDCLK_RATIO_SET25	EQU	2h SHL 18
SDCLK_RATIO_SET3	EQU	3h SHL 18
SDCLK_RATIO_SET35	EQU	4h SHL 18
SDCLK_RATIO_SET4	EQU	5h SHL 18
SDCLK_RATIO_SET45	EQU	6h SHL 18
SDCLK_RATIO_SET5	EQU	7h SHL 18

CNTRL_DRIVE_CLR		EQU	0FC7FFFFFh
CNTRL_DRIVE_SET1	EQU	1h SHL 23
CNTRL_DRIVE_SET2	EQU	2h SHL 23
CNTRL_DRIVE_SET3	EQU	3h SHL 23
CNTRL_DRIVE_SET4	EQU	4h SHL 23
CNTRL_DRIVE_SET5	EQU	5h SHL 23
CNTRL_DRIVE_SET6	EQU	6h SHL 23
CNTRL_DRIVE_SET7	EQU	7h SHL 23

MA_DRIVE_CLR		EQU	0E3FFFFFFh
MA_DRIVE_SET1		EQU	1h SHL 26
MA_DRIVE_SET2		EQU	2h SHL 26
MA_DRIVE_SET3		EQU	3h SHL 26
MA_DRIVE_SET4		EQU	4h SHL 26
MA_DRIVE_SET5		EQU	5h SHL 26
MA_DRIVE_SET6		EQU	6h SHL 26
MA_DRIVE_SET7		EQU	7h SHL 26

MD_DRIVE_CLR		EQU	01FFFFFFFh
MD_DRIVE_SET1		EQU	1h SHL 29
MD_DRIVE_SET2		EQU	2h SHL 29
MD_DRIVE_SET3		EQU	3h SHL 29
MD_DRIVE_SET4		EQU	4h SHL 29
MD_DRIVE_SET5		EQU	5h SHL 29
MD_DRIVE_SET6		EQU	6h SHL 29
MD_DRIVE_SET7		EQU	7h SHL 29


; CPU_MC_MEM_CNTLR2
FAST_RD_MASK_CLR	EQU	0FFFFFFFEh
FAST_RD_MASK_SET	EQU	00000001h

READ_PHASE_CLR		EQU	0FFFFFFFDh
READ_PHASE_SET		EQU	 00000002h

SDCLK_SHIFT_CLR		EQU	0FFFFFFC6h
SDCLK_SHIFT_SET0_5	EQU	1h SHL 3
SDCLK_SHIFT_SET1	EQU	2h SHL 3
SDCLK_SHIFT_SET1_5	EQU	3h SHL 3
SDCLK_SHIFT_SET2	EQU	4h SHL 3
SDCLK_SHIFT_SET2_5	EQU	5h SHL 3
SDCLK_SHIFT_SET3	EQU	6h SHL 3

SDCLK_SHIFT_SET05	EQU	1h SHL 3
SDCLK_SHIFT_SET1	EQU	2h SHL 3
SDCLK_SHIFT_SET15	EQU	3h SHL 3
SDCLK_SHIFT_SET2	EQU	4h SHL 3
SDCLK_SHIFT_SET25	EQU	5h SHL 3
SDCLK_SHIFT_SET3	EQU	6h SHL 3

SDCLK_MASK_CLR		EQU	0FFFFFC3FH
SDCLK_MASK_SET		EQU	000003C0H

SDCLKOUT_MASK_CLR	EQU	0FFFFFBFFH
SDCLKOUT_MASK_SET	EQU	 00000400H

SDCLK_DRIVE_CLR		EQU	0FFFFC7FFh
SDCLK_DRIVE_SET1	EQU	1h SHL 11
SDCLK_DRIVE_SET2	EQU	2h SHL 11
SDCLK_DRIVE_SET3	EQU	3h SHL 11
SDCLK_DRIVE_SET4	EQU	4h SHL 11
SDCLK_DRIVE_SET5	EQU	5h SHL 11
SDCLK_DRIVE_SET6	EQU	6h SHL 11
SDCLK_DRIVE_SET7	EQU	7h SHL 11

SDCLK_FALL_DELAY_CLR	EQU	0FFFF3FFFH
SDCLK_FALL_DEALY_SET1	EQU	1h SHL 14
SDCLK_FALL_DELAY_SET2	EQU	2h SHL 14
SDCLK_FALL_DELAY_SET3	EQU	3h SHL 14

SDCLK_EDGE_DELAY_CLR	EQU	0FFFCFFFFH
SDCLK_EDGE_DEALY_SET1	EQU	1h SHL 16
SDCLK_EDGE_DELAY_SET2	EQU	2h SHL 16
SDCLK_EDGE_DELAY_SET3	EQU	3h SHL 16

; CPU_MC_BANK_CFG
DIMM0_PAGE_CLR		EQU	0FFFFFF0Fh
DIMM0_SIZE_CLR		EQU	0FFFFF0FFh
DIMM0_COMP_CLR		EQU	0FFFFEFFFh
DIMM0_PAGE_SET		EQU	0000070h
DIMM0_SIZE_SET		EQU	0000700h
DIMM0_COMP_SET		EQU	0001000h
DIMM0_MODULE_CLR	EQU	0FFFFBFFFh
DIMM0_MODULE_SET	EQU	00004000h
DIMM_MISSING		EQU	00000070h

; CPU_MC_SYNC_TIM1
CAS_LATENCY_CLR		EQU	08FFFFFFFh
CAS_LATENCY_SET2	EQU	2h SHL 28
CAS_LATENCY_SET3	EQU	3h SHL 28
CAS_LATENCY_SET4	EQU	4h SHL 28
CAS_LATENCY_SET5	EQU	5h SHL 28
CAS_LATENCY_SET6	EQU	6h SHL 28
CAS_LATENCY_SET7	EQU	7h SHL 28

tRCD_CLR			EQU 0FFFF8FFFh
tRCD_SET2			EQU 2h SHL 12
tRCD_SET3			EQU 3h SHL 12
tRCD_SET4			EQU 4h SHL 12
tRCD_SET5			EQU 5h SHL 12
tRCD_SET6			EQU 6h SHL 12
tRCD_SET7			EQU 7h SHL 12

TEST_DATA1		EQU	05A5A5A5Ah
TEST_DATA2		EQU	0DEADBEEFh