bdcfg.inc

X86 GX1 BOOTLOAD代码 ,支持WINCE操作系统!

;***** Copyright (c) 2000 National Semiconductor Corporation ********
;****** All Rights Reserved. ****************************************
;
; File:         bdcfg.inc
;
; Summary:      This file will contain board specific equates and defines
;		that are not in the configurator and the options.inc
;		file. They are here for new features
;
; Contents:     
;
; Author:       Staff
;
; Last Edit:    11/09/2000 08:51:14 by Staff
;
; Notes:        
;
; Revisions:    
;
;********************************************************************
;********************************************************************
; memory setup	- defaults for SCxxxx
;********************************************************************
NUMBER_DIMMS	equ	2
DIMMADDRESS1	equ	0
DIMMADDRESS2	equ	0		


;********************************************************************
; the following entries are for the Disk On Chip (D.O.C)
;********************************************************************
DOC_USED	equ	0		; no D.O.C
DOC_BASE	equ	0		; Linear Base Address of DOC
; The following MUST be in multiples of 8K!
DOC_SIZE	equ	0		; size of DOC in K
DOC_RW		equ	0		; 1=DOCW&DOCR   0=IOW&IOR


;********************************************************************
; IOCS0# and IOCS1# definition
;********************************************************************
IOCS0_USED	equ	0		; used
IOCS0_BASE	equ	0		; io base address
IOCS0_SIZE	equ	0		; size in bytes (1,2,4,8,16,32)
IOCS0_POS_DEC	equ	0	 	; positive decode = 1
IOCS0_RD_EN	equ	0		; read results in CS =1
IOCS0_WR_EN	equ	0		; Write results in CS =1

IOCS1_USED	equ	0		; used
IOCS1_BASE	equ	0		; io base address
IOCS1_SIZE	equ	0		; size in bytes  (1,2,4,8,16,32)
IOCS1_POS_DEC	equ	0	 	; positive decode = 1
IOCS1_RD_EN	equ	0		; read results in CS =1
IOCS1_WR_EN	equ	0		; Write results in CS =1


;*******************************************************************
; The following entries are for the PMR and MCR register initial 
; settings - Example values are for SC1200/Carmel
;*******************************************************************
; For A rev chips
	; Parallel Port, IDE or TFT/CRT, AC97,
	; Video Port, IOR/IOW, AB2, SP2, SP1,
	; TRDE, GPIO20, SP3, GPIO17, GPIO19,
;			 3	   2	     1	       0
;			10987654321098765432109876543210
USER_PMR_A	equ	00000010010011110011000000000001b
; For B rev chips
	; Parallel Port, IDE,  AC97,   IOR/IOW,
	; AB2, SP2, SP1, LPC, GPIO01, TRDE, INTC
	; IR, GPIO20, PC_BEEP
;			 3	   2	     1	       0
;			10987654321098765432109876543210
USER_PMR_B	equ	00000010000011110010100000010001b


; Miscellaneous Configuration Register (MCR, offset 34h)
	; Bit 13 0 => 27Mhz clock, 1 => 25Mhz clock
	;	SC1200 typically uses 27Mhz, SC3200 and SC2200 typically use 25Mhz
;                3         2         1         0
;               10987654321098765432109876543210
USER_MCR    equ 00000000000000000000000000000000b	; 27 Mhz
;USER_MCR    equ 00000000000000000010000000000000b	; 25 Mhz

;********************************************************************
; access bus memory devices are on
;********************************************************************
MEM_ACCESS_BUS	EQU	ACCESS_BUS1_DEVICE	; access bus 1
DDC_ACCESS_BUS	EQU	ACCESS_BUS1_DEVICE	; access bus 1

;********************************************************************
; defaults for CMOS/SETUP
;********************************************************************

DEFAULT_UART1_CONFIG	EQU	TVALUE_UART_CONFIG_3F8	; 3f8,irq 4
DEFAULT_UART2_CONFIG	EQU	TVALUE_UART_CONFIG_2F8	; 2f8,irq 3
DEFAULT_UART3_CONFIG	EQU	TVALUE_UART_CONFIG_3E8	; 3e8,irq 4

IF LPTMODE EQ 0
DEFAULT_LPTA_PORT	EQU	TVALUE_LPT_PORT_DIS	; disabled
DEFAULT_LPTA_MODE	EQU	TVALUE_LPT_MODE_SPP
ELSE
DEFAULT_LPTA_PORT	EQU	TVALUE_LPT_PORT_378	; 378
IF LPTMODE EQ 1
DEFAULT_LPTA_MODE	EQU	TVALUE_LPT_MODE_SPP
ELSE
DEFAULT_LPTA_MODE	EQU	TVALUE_LPT_MODE_PS2
ENDIF
ENDIF

DEFAULT_LPTA_IRQ	EQU	7
DEFAULT_LPTA_DMA	EQU	4

DEFAULT_AUDIO_ENABLE	EQU	TVALUE_AUDIO_ENABLE
DEFAULT_AUD_BASE	EQU	TVALUE_AUD_BASE_220
DEFAULT_AUD_IRQ		EQU	TVALUE_AUD_IRQ_5
DEFAULT_AUD_DMA8	EQU	TVALUE_AUD_DMA8_1
DEFAULT_AUD_DMA16	EQU	TVALUE_AUD_DMA16_5
DEFAULT_USB_ENABLE 	EQU	TVALUE_USB_ENABLE
DEFAULT_LEGACY_USB_ENABLE 	EQU	TVALUE_LEGACY_USB_DISABLE

IF TV EQ 0
DEFAULT_TV_OUTPUT	EQU	TVALUE_TV_OUTPUT_NONE
ELSE
IF TVOUTPUT eq 1
DEFAULT_TV_OUTPUT	EQU	TVALUE_TV_OUTPUT_SVIDEO
ELSE
DEFAULT_TV_OUTPUT	EQU	TVALUE_TV_OUTPUT_COMP
ENDIF
ENDIF

IF TVMODE eq 1
DEFAULT_TV_FORMAT	EQU	TVALUE_TV_FORMAT_PAL
ELSE
DEFAULT_TV_FORMAT	EQU	TVALUE_TV_FORMAT_NTSC
ENDIF

IF TVFORMAT EQ 1
DEFAULT_TV_MODE		EQU	TVALUE_TV_MODE_800	
ELSE
DEFAULT_TV_MODE		EQU	TVALUE_TV_MODE_640	
ENDIF

DEFAULT_TV_HPOS		EQU	121
DEFAULT_TV_VPOS		EQU	1

DEFAULT_LPC_UART1	EQU	TVALUE_UART_CONFIG_DIS
DEFAULT_LPC_UART2	EQU	TVALUE_UART_CONFIG_DIS
DEFAULT_LPC_LPT_PORT	EQU	TVALUE_LPT_PORT_278
DEFAULT_LPC_LPT_MODE	EQU	TVALUE_LPT_MODE_SPP
DEFAULT_LPC_LPT_IRQ	EQU	0
DEFAULT_LPC_LPT_DMA	EQU	4	; none

DEFAULT_MEM_OPTIMIZE	EQU	AUTO_MEM_TIME
DEFAULT_CACHE_ENABLE	EQU	CACHEON


;********************************************************************
; GPIOS used for 9211 - the defaults shown are for the dorado board
;********************************************************************
; SCx2xx Gpios connected to 9211
CLOCK9211CFG		EQU	007h	;gpio 7, clock output to 9211
DATAIN9211CFG		EQU	012h	;gpio 18, data output to 9211
DATAOUT9211CFG		EQU	00bh	;gpio 11, data input from 9211
CS9211CFG		EQU	009h	;gpio 9, chip select output to 9211

; 9211 gpios used to determine resolution - these MUST be in ascending order
LCDRESGPIO1		EQU	00h
LCDRESGPIO2		EQU	01h
LCDRESGPIO3		EQU	02h
LCDRESGPIO4		EQU	04h


;********************************************************************
; GPIOS used for DDC - the defaults shown are for the dorado board
;********************************************************************
DDC_CLOCKCFG		EQU	007h	;Clock Line  - gpio 7
DDC_DATACFG		EQU	012h	;Data Line   - gpio 18
DDC_CSCFG		EQU	009h	;Chip Select - gpio 9

;********************************************************************
; default settings for the boot selection in setup and int 19
;********************************************************************
	; uncomment the following item to add boot selection in
	; setup and CMOS
;NUMBER_BOOT_ITEMS	EQU	4

	; Warning: booting from any hard drive other than the first
	;  (80h)is highly dependant on the operating system.
HIGHEST_BOOT_HD		EQU	2

; if floppy  code installed
if FDDINSTALL
; if boot from floppy 1st
if BOOTORDER
DEFAULT_BOOT_1		EQU	TVALUE_BOOT_FLOPPY
DEFAULT_BOOT_2		EQU	TVALUE_BOOT_HD_1
DEFAULT_BOOT_3		EQU	TVALUE_BOOT_NONE
DEFAULT_BOOT_4		EQU	TVALUE_BOOT_NONE
DEFAULT_BOOT_5		EQU	TVALUE_BOOT_NONE
DEFAULT_BOOT_6		EQU	TVALUE_BOOT_NONE
DEFAULT_BOOT_7		EQU	TVALUE_BOOT_NONE
DEFAULT_BOOT_8		EQU	TVALUE_BOOT_NONE
else
; boot from floppy last
DEFAULT_BOOT_1		EQU	TVALUE_BOOT_HD_1
DEFAULT_BOOT_2		EQU	TVALUE_BOOT_FLOPPY
DEFAULT_BOOT_3		EQU	TVALUE_BOOT_NONE
DEFAULT_BOOT_4		EQU	TVALUE_BOOT_NONE
DEFAULT_BOOT_5		EQU	TVALUE_BOOT_NONE
DEFAULT_BOOT_6		EQU	TVALUE_BOOT_NONE
DEFAULT_BOOT_7		EQU	TVALUE_BOOT_NONE
DEFAULT_BOOT_8		EQU	TVALUE_BOOT_NONE
endif
else
; no floppy support installed
DEFAULT_BOOT_1		EQU	TVALUE_BOOT_HD_1
DEFAULT_BOOT_2		EQU	TVALUE_BOOT_NONE
DEFAULT_BOOT_3		EQU	TVALUE_BOOT_NONE
DEFAULT_BOOT_4		EQU	TVALUE_BOOT_NONE
DEFAULT_BOOT_5		EQU	TVALUE_BOOT_NONE
DEFAULT_BOOT_6		EQU	TVALUE_BOOT_NONE
DEFAULT_BOOT_7		EQU	TVALUE_BOOT_NONE
DEFAULT_BOOT_8		EQU	TVALUE_BOOT_NONE
endif		




;*******************************************************************
; do not make modifications below this line
; these values are determined by the entries above !!!!
;*******************************************************************

; PMR Value for DOC sets Bits 7 and 2 of PMR if DOC is used
DOC_PMR		equ	(DOC_USED shl 7) OR (DOC_RW shl 2)
; LPC PMR VALUES rev A & B
LPC_PMR_A	equ	(LPC SHL 12)
LPC_PMR_B	equ	(LPC SHL 12) or (LPC SHL 20)

MTEST_PMR	equ	(MDEBUG shl 28) or (MDEBUG shl 29)
; Final PMR Values to Use
PMR_A_VALUE	equ	USER_PMR_A or DOC_PMR or LPC_PMR_A or MTEST_PMR
PMR_B_VALUE	equ	USER_PMR_B or DOC_PMR or LPC_PMR_B or MTEST_PMR

; DOC enable bits for F0  7F
DOC_F0_7F	equ	(DOC_USED) or (DOC_USED shl 1) or (DOC_USED shl 2);
; DOC Address Mask for F0 7C-7D
IF NOT DOC_SIZE EQ 0
 DOC_F0_7C_MASK	equ	((DOC_SIZE * 1024) - 1) shr 13
ELSE
 DOC_F0_7C_MASK	equ	0
ENDIF

; IOCSx control byte
IF IOCS0_USED EQ 1
  IOCS0_CONTROL equ	((IOCS0_SIZE -1) and 01fH) or (IOCS0_RD_EN SHL 5) \
  		or (IOCS0_WR_EN SHL 6) or (IOCS0_POS_DEC SHL 7)
ELSE
  IOCS0_CONTROL	equ 	0
ENDIF	

IF IOCS1_USED EQ 1
  IOCS1_CONTROL equ	((IOCS1_SIZE -1) and 01fH) or (IOCS1_RD_EN SHL 5) \
  		or (IOCS1_WR_EN SHL 6) or (IOCS1_POS_DEC SHL 7)
ELSE
  IOCS1_CONTROL	equ 	0
ENDIF