📄 mcbsp_inti.c
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/******************************************************************************/
/* Copyright 2004 by SEED Electronic Technology LTD. */
/* All rights reserved. SEED Electronic Technology LTD. */
/* Restricted rights to use, duplicate or disclose this code are */
/* granted through contract. */
/******************************************************************************/
#include <stdio.h>
#include <csl.h>
#include <csl_mcbsp.h>
#include <csl_gpio.h>
#include "DEC6713.h"
#include "comm.h"
#include "type.h"
/*****************************************************************************/
#define FRAMLONGTH 0x80
#define DataLongth 0x7c
/////////////////////
MCBSP_Handle hMcbsp;
unsigned short RevBuffer[FRAMLONGTH];
/*******************************************/
//系统缓冲区的定义：
//系统缓冲区的定义：
//第1个字节 ：数据准备好
//第2个字节 ：出现故障
//第3个字节 ：有新帧
//第4个字节 ：中断超时
//第5个字节 ：较验出错
#define RECEIVE_RDY 0x1
#define MCBSP_ERR 0x2
#define RECEIVE_NEW 0x3
#define INT_ERR 0x4
#define CHECK_ERROR 0x5
unsigned short sys_statbuff[6];
unsigned short mcbspx[FRAMLONGTH];
unsigned short mcbspr[FRAMLONGTH];
//////////////////
int datarevlength=0,timeout,mod,s,number=0,k;
/*********************************************************/
extern far void vectors();
/********************************************************************************/
static MCBSP_Config ConfigLoopback = {
/* Serial Port Control Register (SPCR) */
MCBSP_SPCR_RMK(
MCBSP_SPCR_FREE_YES, /* Serial clock free running mode(FREE)
MCBSP_SPCR_FREE_NO - During emulation halt,SOFT bit
determines operation of McBSP.
MCBSP_SPCR_FREE_YES - During emulation halt, serial
clocks continue to run. */
MCBSP_SPCR_SOFT_YES, /* Serial clock emulation mode(SOFT)
MCBSP_SPCR_SOFT_NO - In conjunction with FREE = 0,
serial port clock stops immediately during
emulation halt,thus aborting any transmissions.
MCBSP_SPCR_SOFT_YES - In conjunction with FREE = 0,
during emulation halt, serial port clock stops
after completion of current transmission. */
MCBSP_SPCR_FRST_YES, /* Frame sync generator reset(FRST)
MCBSP_SPCR_FRST_YES /MCBSP_SPCR_FRST_0 - Frame sync
generation logic is reset.
MCBSP_SPCR_FRST_NO /MCBSP_SPCR_FRST_1 - Frame sync
signal is generated after eight CLKG clocks. */
MCBSP_SPCR_GRST_YES, /* Sample rate generator reset(GRST)
MCBSP_SPCR_GRST_YES /MCBSP_SPCR_GRST_0 - Reset
MCBSP_SPCR_GRST_NO /MCBSP_SPCR_GRST_1 -Out of reset*/
MCBSP_SPCR_XINTM_XRDY,/* Transmit interrupt mode(XintM)
MCBSP_SPCR_XintM_XRDY - Xint driven by XRDY
MCBSP_SPCR_XintM_EOS - Xint generated by
end-of-subframe in multichannel operation
MCBSP_SPCR_XintM_FRM - Xint generated by a new frame
synchronization
MCBSP_SPCR_XintM_XSYNCERR - Xint generated by XSYNCERR
*/
MCBSP_SPCR_XSYNCERR_NO,/* Transmit synchronization error
MCBSP_SPCR_XSYNCERR_NO /MCBSP_SPCR_XSYNCERR_0 - No
frame synchronization error
MCBSP_SPCR_XSYNCERR_YES /MCBSP_SPCR_XSYNCERR_1 - Frame
synchronization error detected by McBSP */
MCBSP_SPCR_XRST_YES, /* Transmitter reset(XRST). This resets or enables
transmitter.
MCBSP_SPCR_XRST_YES /MCBSP_SPCR_XRST_0 - Serial port
transmitter is disabled and is in reset state.
MCBSP_SPCR_XRST_NO /MCBSP_SPCR_XRST_1 - Serial port
transmitter is enabled. */
MCBSP_SPCR_DLB_OFF, /* Digital loopback(DLB) mode
MCBSP_SPCR_DLB_OFF - DLB Disabled
MCBSP_SPCR_DLB_ON - DLB Enabled */
MCBSP_SPCR_RJUST_RZF,/*Receive data sign-extension and justification mode(RJUST)
MCBSP_SPCR_RJUST_RZF - Right-justify and zero-fill
MSBs in DRR.
MCBSP_SPCR_RJUST_RSE - Right-justify and sign-extend
MSBs in DRR.
MCBSP_SPCR_RJUST_LZF - Left-justify and zero-fill
LSBs in DRR. */
MCBSP_SPCR_CLKSTP_DISABLE,/* Clock stop(CLKSTP) mode
MCBSP_SPCR_CLKSTP_DISABLE - Disabled. Normal
clocking enabled for non-SPI mode.
MCBSP_SPCR_CLKSTP_NODELAY -Clock starts without delay.
MCBSP_SPCR_CLKSTP_DELAY - Clock starts with delay.*/
MCBSP_SPCR_DXENA_OFF,/* DX Enabler(DXENA) -Extra delay for DX turn-on time.
Only first bit of data is delayed.
MCBSP_SPCR_DXENA_OFF - DX enabler is off.
MCBSP_SPCR_DXENA_ON - DX enabler is on. */
MCBSP_SPCR_RINTM_RRDY,/* Receive interrupt(Rint) mode
MCBSP_SPCR_RintM_RRDY - Rint driven by RRDY
MCBSP_SPCR_RintM_EOS - Rint generated by
end-of-subframe in multichannel operation
MCBSP_SPCR_RintM_FRM - Rint generated by a new frame
synchronization
MCBSP_SPCR_RintM_RSYNCERR -Rint generated by RSYNCERR*/
MCBSP_SPCR_RSYNCERR_NO,/* Receive synchronization error(RSYNCERR)
MCBSP_SPCR_RSYNCERR_NO /MCBSP_SPCR_RSYNCERR_0 - No
frame synchronization error
MCBSP_SPCR_RSYNCERR_YES /MCBSP_SPCR_RSYNCERR_1 - Frame
synchronization error detected by McBSP */
MCBSP_SPCR_RRST_YES /* Receiver reset(RRST). This resets or enables
receiver.
MCBSP_SPCR_RRST_YES /MCBSP_SPCR_RRST_0 - Serial
port receiver is disabled and is in reset state.
MCBSP_SPCR_RRST_NO /MCBSP_SPCR_RRST_1 - Serial
port receiver is enabled. */
),
/* Receive Control Register (RCR) */
MCBSP_RCR_RMK(
MCBSP_RCR_RPHASE_SINGLE, /* Receive phases
MCBSP_RCR_RPHASE_SINGLE - Single phase frame
MCBSP_RCR_RPHASE_DUAL - Dual phase frame */
MCBSP_RCR_RFRLEN2_OF(0), /* Receive frame length in phase 2(RFRLEN2)
000 0000b: 1 word per phase
000 0001b: 2 words per phase
. . . . . . . . . . . .
111 1111b: 128 words per phase */
MCBSP_RCR_RWDLEN2_8BIT,/* Receive element length in phase 2(RWDLEN2)
MCBSP_RCR_RWDLEN2_8BIT - 8 bits
MCBSP_RCR_RWDLEN2_12BIT - 12 bits
MCBSP_RCR_RWDLEN2_16BIT - 16 bits
MCBSP_RCR_RWDLEN2_20BIT - 20 bits
MCBSP_RCR_RWDLEN2_24BIT - 24 bits
MCBSP_RCR_RWDLEN2_32BIT - 32 bits */
MCBSP_RCR_RCOMPAND_MSB,/* Receive companding mode (RCOMPAND)
MCBSP_RCR_RCOMPAND_MSB - No companding.Data
transfer starts with MSB first.
MCBSP_RCR_RCOMPAND_8BITLSB - No companding,
8-bit data. Transfer starts with LSB first.
Applicable to 8-bit data or 32-bit data in
data reversal mode.
MCBSP_RCR_RCOMPAND_ULAW - Compand using m-law for
receive data. Applicable to 8-bit data only
MCBSP_RCR_RCOMPAND_ALAW - Compand using A-law for
receive data. Applicable to 8-bit data only */
MCBSP_RCR_RFIG_YES, /* Receive frame ignore(RFIG)
MCBSP_RCR_RFIG_NO - Unexpected receive frame
synchronization pulses restart the transfer.
MCBSP_RCR_RFIG_YES - Unexpected receive frame
synchronization pulses are ignored. */
MCBSP_RCR_RDATDLY_1BIT,/* Receive data delay(RDATDLY)
MCBSP_RCR_RDATDLY_0BIT - 0 bit data delay
MCBSP_RCR_RDATDLY_1BIT - 1 bit data delay
MCBSP_RCR_RDATDLY_2BIT - 2 bit data delay */
MCBSP_RCR_RFRLEN1_OF(0), /* Receive frame length in phase 1(RFRLEN1)
000 0000b: 1 word per phase
000 0001b: 2 words per phase
. . . . . . . . . . . .
111 1111b: 128 words per phase */
MCBSP_RCR_RWDLEN1_16BIT,/* Receive element length in phase 1(RWDLEN1)
MCBSP_RCR_RWDLEN1_8BIT - 8 bits
MCBSP_RCR_RWDLEN1_12BIT - 12 bits
MCBSP_RCR_RWDLEN1_16BIT - 16 bits
MCBSP_RCR_RWDLEN1_20BIT - 20 bits
MCBSP_RCR_RWDLEN1_24BIT - 24 bits
MCBSP_RCR_RWDLEN1_32BIT - 32 bits */
MCBSP_RCR_RWDREVRS_DISABLE/* Receive 32-bit bit reversal feature.(RWDREVRS)
MCBSP_RCR_RWDREVRS_DISABLE -32 bit reversal disabled
MCBSP_RCR_RWDREVRS_ENABLE -32 bit reversal enabled.
32-bit data is received LSB first.
RWDLEN should be set for 32-bit operation.
RCOMPAND should be set to 01b else operation
is undefined. */
),
/* Transmit Control Register (XCR) */
MCBSP_XCR_RMK(
MCBSP_XCR_XPHASE_SINGLE,/* Transmit phases
MCBSP_XCR_XPHASE_SINGLE - Single phase frame
MCBSP_XCR_XPHASE_DUAL - Dual phase frame */
MCBSP_XCR_XFRLEN2_OF(0),/* Transmit frame length in phase 2(XFRLEN2)
000 0000b: 1 word per phase
000 0001b: 2 words per phase
. . . . . . . . . . . .
111 1111b: 128 words per phase */
MCBSP_XCR_XWDLEN2_8BIT, /* Transmit element length in phase 2
MCBSP_XCR_XWDLEN2_8BIT - 8 bits
MCBSP_XCR_XWDLEN2_12BIT - 12 bits
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