altera_avalon_16_bit_vga.vhd

VGA控制器源码

-- ================================================================================
-- (c) 2005 Altera Corporation. All rights reserved.
-- Altera products are protected under numerous U.S. and foreign patents, maskwork
-- rights, copyrights and other intellectual property laws.
-- 
-- This reference design file, and your use thereof, is subject to and governed
-- by the terms and conditions of the applicable Altera Reference Design License
-- Agreement (either as signed by you, agreed by you upon download or as a
-- "click-through" agreement upon installation andor found at www.altera.com).
-- By using this reference design file, you indicate your acceptance of such terms
-- and conditions between you and Altera Corporation.  In the event that you do
-- not agree with such terms and conditions, you may not use the reference design
-- file and please promptly destroy any copies you have made.
-- 
-- This reference design file is being provided on an "as-is" basis and as an
-- accommodation and therefore all warranties, representations or guarantees of
-- any kind (whether express, implied or statutory) including, without limitation,
-- warranties of merchantability, non-infringement, or fitness for a particular
-- purpose, are specifically disclaimed.  By making this reference design file
-- available, Altera expressly does not recommend, suggest or require that this
-- reference design file be used in combination with any other product not
-- provided by Altera.
--================================================================================

-- altera_avalon_16_bit_vga.vhd
--
--
-- This design provides an interface to the Alcahest VGA daughter card.
-- The design comprises of an 8-bit VGA driver with Avalon bus interfaces.  There are a total of
-- three Avalon interfaces.
-- 1) The DMA Master Interface
--    - The design contains a DMA controller which loads images from memory (SRAM,SDRAM) line by  
--      line into a line buffer.  
-- 2) The Configuration Slave Interface
--    - The configuration slave interface provides a means of setting up the VGA driver and the
--      DMA controller. It allows you to configure the size of the image, it's location in memory
--      and whether or not IRQs should be enabled.
-- 3) The Palette RAM Slave Interface
--    - This design contains a palette RAM which converts 8-bit internal pixels to 24-bit pixels to
--      drive to the DAC.  Each 8-bit pixel provides an index to the palette RAM. 
-- 
-- The VGA timing circuitry needs to be driven at 25MHz.  However, the DMA controller should 
-- ideally be driven a fast as possible to provide the best bandwidth usage.  The "clk" signal
-- provideds the clock to the DMA controller and the register bank.  The "clock25" signal drives
-- the timing circuitry inside the VGA driver.  While the vga_clk signal is fed directly to an
-- output pin to drive the DAC.  This signal should also be 25MHz and should be synchronous to
-- clock25 (you could even connect it to clock25).

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY altera_avalon_16_bit_vga IS
PORT (
	-- common signals
	resetn			: IN std_logic; -- system reset
	clk			: IN std_logic; -- Avalon clock
	clock25			: IN std_logic;	-- VGA driver clock
	vga_clk			: IN std_logic; -- 25MHz clock to drive to DAC
	
	-- slave port 1, config
	chipselect_config	: IN std_logic;
	address_config		: IN std_logic_vector(2 downto 0);
	read_config		: IN std_logic;
	irq			: OUT std_logic;
	readdata_config		: OUT std_logic_vector(31 downto 0);
	write_config		: IN std_logic;
	writedata_config	: IN std_logic_vector(31 downto 0);

	-- DMA signals		
	read_to_sram		: OUT std_logic;
	address_to_sram		: OUT std_logic_vector(31 downto 0);
	data_from_sram		: IN std_logic_vector(31 downto 0);
	waitrequest		: IN std_logic;
	readdatavalid		: IN std_logic;

	-- VGA outputs
	vga_clock_external	: OUT std_logic;
	hsync			: OUT std_logic;
	vsync			: OUT std_logic;
	M1			: OUT std_logic;
	M2			: OUT std_logic;
	sync_n			: OUT std_logic;
	sync_t			: OUT std_logic;
	blank_n			: OUT std_logic;
	R			: OUT std_logic_vector(7 downto 0);
	G			: OUT std_logic_vector(7 downto 0);
	B			: OUT std_logic_vector(7 downto 0)
);
END altera_avalon_16_bit_vga;

ARCHITECTURE rtl OF altera_avalon_16_bit_vga IS

COMPONENT image_dma 
	PORT (
		resetn			: IN std_logic;
		clk			: IN std_logic;
		image_address		: IN std_logic_vector(31 downto 0);
		mode			: IN std_logic;
		hsync			: IN std_logic;
		vblank			: IN std_logic;
		num_pixels_per_line	: IN std_logic_vector(9 downto 0);
		waitrequest		: IN std_logic;
		readdatavalid		: IN std_logic;
		address_to_sram		: OUT std_logic_vector(31 downto 0);
		data_from_sram		: IN std_logic_vector(31 downto 0);
		read_to_sram		: OUT std_logic;
		data_to_buffer		: OUT std_logic_vector(31 downto 0);
		address_to_buffer	: OUT std_logic_vector(8 downto 0);
		write_to_buffer		: OUT std_logic
		);
END COMPONENT;

COMPONENT line_buffer 
	PORT
	(
		data		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		wren		: IN STD_LOGIC  := '1';
		wraddress	: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
		rdaddress	: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
		wrclock		: IN STD_LOGIC ;
		rdclock		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
	);
END COMPONENT;

COMPONENT vga_register_bank 
	PORT (
		resetn			: IN std_logic;
		clk			: IN std_logic;
		chipselect		: IN std_logic;
		address			: IN std_logic_vector(2 downto 0);
		read			: IN std_logic;
		set_picture_end_irq	: IN std_logic;
		irq			: OUT std_logic;
		readdata		: OUT std_logic_vector(31 downto 0);
		write			: IN std_logic;
		writedata		: IN std_logic_vector(31 downto 0);
		image_address		: OUT std_logic_vector(31 downto 0);
		size			: OUT std_logic_vector(31 downto 0);
		control			: OUT std_logic_vector(31 downto 0)
	);
END COMPONENT;

COMPONENT vga_driver  
	PORT (
		reset_n			: IN std_logic;
		clk			: IN std_logic; -- Avalon clock
		clock25			: IN std_logic;
		vga_clk			: IN std_logic;
		
		-- control signals
		enable_irq		: IN std_logic;
		enable			: IN std_logic;
		mode			: IN std_logic;

		-- video memory signals
		video_data		: IN std_logic_vector(15 downto 0);
		video_address		: OUT std_logic_vector(31 downto 0);

		-- parameter signals from avalon slave interface
		num_lines		: IN std_logic_vector(9 downto 0);
		num_pixels_per_line	: IN std_logic_vector(9 downto 0);

		set_picture_end_irq	: OUT std_logic;

		-- blanking outputs to any external logic that might need it
		hblank			: OUT std_logic;
		vblank			: OUT std_logic;

		-- outputs to VGA daughter card
		clockext		: OUT std_logic;
		sync_n			: OUT std_logic;
		sync_t			: OUT std_logic;
		blank_n			: OUT std_logic;
		M1			: OUT std_logic;
		M2			: OUT std_logic;
		vsync			: OUT std_logic;
		hsync			: OUT std_logic;
		R			: OUT std_logic_vector(7 downto 0);
		G			: OUT std_logic_vector(7 downto 0);
		B			: OUT std_logic_vector(7 downto 0)
	);
END COMPONENT;

	SIGNAL gnd		: std_logic_vector(31 downto 0);
	SIGNAL hsync_internal		: std_logic;
	SIGNAL num_lines		: std_logic_vector(9 downto 0);
	SIGNAL num_pixels_per_line	: std_logic_vector(9 downto 0);
	SIGNAL enable			: std_logic;
	SIGNAL enable_irq		: std_logic;
	SIGNAL image_address		: std_logic_vector(31 downto 0);
	SIGNAL set_frame_fill_irq	: std_logic;
	SIGNAL set_picture_end_irq	: std_logic;
	SIGNAL size			: std_logic_vector(31 downto 0);
	SIGNAL control			: std_logic_vector(31 downto 0);
	SIGNAL video_data		: std_logic_vector(15 downto 0);
	SIGNAL video_address		: std_logic_vector(31 downto 0);
	SIGNAL vblank			: std_logic;
	
	SIGNAL mode	: std_logic;

	SIGNAL address_to_buffer	: std_logic_vector(8 downto 0);
	SIGNAL write_to_buffer		: std_logic;
	SIGNAL data_to_buffer		: std_logic_vector(31 downto 0);

BEGIN

gnd <= (others => '0');

hsync <= hsync_internal;

config: vga_register_bank
PORT MAP (
	resetn			=> resetn,
	clk			=> clk,
	chipselect		=> chipselect_config,
	address			=> address_config,
	read			=> read_config,
	set_picture_end_irq	=> set_picture_end_irq,
	irq			=> irq,
	readdata		=> readdata_config,	
	write			=> write_config,
	writedata		=> writedata_config,
	image_address		=> image_address,
	size			=> size,
	control			=> control
);

num_lines <= size(9 downto 0);
num_pixels_per_line <= size(25 downto 16);
enable <= control(0);
mode <= control(1);
enable_irq <= control(2);

vga: vga_driver
PORT MAP (
	reset_n			=> resetn,
	clk		=> clk,
	clock25			=> clock25,
	vga_clk			=> vga_clk,
	enable_irq		=> enable_irq,
	enable			=> enable,
	mode                    => mode,
	video_data		=> video_data,
	video_address		=> video_address,
	num_lines		=> num_lines,
	num_pixels_per_line	=> num_pixels_per_line,
	set_picture_end_irq	=> set_picture_end_irq,
	hblank			=> open,
	vblank			=> vblank,
	clockext		=> vga_clock_external,
	sync_n			=> sync_n,
	sync_t			=> sync_t,
	blank_n			=> blank_n,
	M1			=> M1,
	M2			=> M2,
	vsync			=> vsync,
	hsync			=> hsync_internal,
	R			=> R,
	G			=> G,
	B			=> B
);

image_memory: line_buffer
PORT MAP (
	data		=> data_to_buffer,
	wren		=> write_to_buffer,
	wraddress	=> address_to_buffer,
	rdaddress	=> video_address(9 downto 0),
	wrclock		=> clk,
	rdclock		=> clock25,
	q		=> video_data
);

the_image_dma: image_dma
PORT MAP (
	resetn			=> resetn,
	clk			=> clk,
	image_address		=> image_address,
	mode                    => mode,
	hsync			=> hsync_internal,
	vblank			=> vblank,
	num_pixels_per_line	=> num_pixels_per_line,
	waitrequest		=> waitrequest,
	readdatavalid		=> readdatavalid,
	address_to_sram		=> address_to_sram,
	data_from_sram		=> data_from_sram,
	read_to_sram		=> read_to_sram,
	data_to_buffer		=> data_to_buffer,
	address_to_buffer	=> address_to_buffer,
	write_to_buffer		=> write_to_buffer
	);
END rtl;