os_cpu_a.lst
来自「称植到lpc2124上的UCOS2.85版 是本人初学移植和ARM的成果 可」· LST 代码 · 共 825 行 · 第 1/3 页
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825 行
ARM Macro Assembler Page 1
1 00000000 ;*******************************************************
*************************************************
2 00000000 ; uC/OS-II
3 00000000 ; The Real-Time
Kernel
4 00000000 ;
5 00000000 ; (c) Copyright 1992-2005,
Micrium, Weston, FL
6 00000000 ; All Rights Re
served
7 00000000 ;
8 00000000 ; Generic ARM
Port
9 00000000 ;
10 00000000 ; File : OS_CPU_A.ASM
11 00000000 ; Version : V2.00(Rev)
12 00000000 ; By : Jean J. Labrosse
13 00000000 ; Rev By : leafboy(2006.12.16-2006.12.28)
14 00000000 ;
15 00000000 ; For : ARM7 or ARM9
16 00000000 ; Mode : ARM or Thumb
17 00000000 ; Toolchain : KEIL's RV V3.03A and higher
18 00000000 ;*******************************************************
*************************************************
19 00000000
20 00000000
21 00000000 00000000
OS_TASK_SW_HOOK
EQU 0
22 00000000
23 00000000 00000001
ASM_KEILRV
EQU 1
24 00000000
25 00000000 ;--------------------------------
26 00000000 ;- ARM Core Mode and Status Bits
27 00000000 ;--------------------------------
28 00000000
29 00000000 00000010
ARM_MODE_USER
EQU 0x10
30 00000000 00000011
ARM_MODE_FIQ
EQU 0x11
31 00000000 00000012
ARM_MODE_IRQ
EQU 0x12
32 00000000 00000013
ARM_MODE_SVC
EQU 0x13
33 00000000 00000017
ARM_MODE_ABORT
EQU 0x17
34 00000000 0000001B
ARM_MODE_UNDEF
EQU 0x1B
35 00000000 0000001F
ARM_MODE_SYS
ARM Macro Assembler Page 2
EQU 0x1F
36 00000000
37 00000000 00000080
I_BIT EQU 0x80
38 00000000 00000040
F_BIT EQU 0x40
39 00000000 00000020
T_BIT EQU 0x20
40 00000000
41 00000000 EXTERN OSRunning ; External referenc
es
42 00000000 EXTERN OSPrioCur
43 00000000 EXTERN OSPrioHighRdy
44 00000000 EXTERN OSTCBCur
45 00000000 EXTERN OSTCBHighRdy
46 00000000 EXTERN OSIntNesting
47 00000000 EXTERN OSIntExit
48 00000000 EXTERN OSTaskSwHook
49 00000000
50 00000000
51 00000000 EXPORT OS_CPU_SR_Save ; Functions decl
ared in this file
52 00000000 EXPORT OS_CPU_SR_Restore
53 00000000 EXPORT OSStartHighRdy
54 00000000 EXPORT OSCtxSw
55 00000000 EXPORT OSIntCtxSw ; OSIntCtxSw() for
OSIntExit() @ os_co
re.c as null
56 00000000
57 00000000 ;*******************************************************
**************************************************
58 00000000 ; CRITICAL SECTION MET
HOD 3 FUNCTIONS
59 00000000 ;
60 00000000 ; Description: Disable/Enable interrupts by preserving t
he state of interrupts. Generally speaking you
61 00000000 ; would store the state of the interrupt di
sable flag in the local variable 'cpu_sr' and then
62 00000000 ; disable interrupts. 'cpu_sr' is allocate
d in all of uC/OS-II's functions that need to
63 00000000 ; disable interrupts. You would restore th
e interrupt disable state by copying back 'cpu_sr'
64 00000000 ; into the CPU's status register.
65 00000000 ;
66 00000000 ; Prototypes : OS_CPU_SR OS_CPU_SR_Save(void);
67 00000000 ; void OS_CPU_SR_Restore(OS_CPU_S
R cpu_sr);
68 00000000 ;
69 00000000 ;
70 00000000 ; Note(s) : 1) These functions are used in general li
ke this:
71 00000000 ;
72 00000000 ; void Task (void *p_arg)
73 00000000 ; {
74 00000000 ; #if OS_CRITICAL_METHOD == 3 /
* Allocate storage for CPU status register */
75 00000000 ; OS_CPU_SR cpu_sr;
76 00000000 ; #endif
77 00000000 ;
ARM Macro Assembler Page 3
78 00000000 ; :
79 00000000 ; :
80 00000000 ; OS_ENTER_CRITICAL(); /
* cpu_sr = OS_CPU_SaveSR(); */
81 00000000 ; :
82 00000000 ; :
83 00000000 ; OS_EXIT_CRITICAL(); /
* OS_CPU_RestoreSR(cpu_sr); */
84 00000000 ; :
85 00000000 ; :
86 00000000 ; }
87 00000000 ;
88 00000000 ; 2) OS_CPU_SaveSR() is implemented as reco
mmended by Atmel's application note:
89 00000000 ;
90 00000000 ; "Disabling Interrupts at Processor
Level"
91 00000000 ;*******************************************************
**************************************************
92 00000000 IF (ASM_KEILRV > 0)
93 00000000 PRESERVE8
94 00000000
95 00000000 AREA |.text|, CODE, READONLY
96 00000000 ARM
97 00000000 ELSE
100 ENDIF
101 00000000
102 00000000 OS_CPU_SR_Save
103 00000000 E10F0000 MRS R0,CPSR ; Set IRQ and FIQ b
its in CPSR to disa
ble all interrupts
104 00000004 E38010C0 ORR R1,R0,#(I_BIT | F_BIT)
105 00000008 E121F001 MSR CPSR_c,R1
106 0000000C E12FFF1E BX LR ; Disabled, return
the original CPSR c
ontents in R0
107 00000010
108 00000010
109 00000010 OS_CPU_SR_Restore
110 00000010 E121F000 MSR CPSR_c,R0
111 00000014 E12FFF1E BX LR
112 00000018
113 00000018
114 00000018 ;*******************************************************
**************************************************
115 00000018 ; START MULTITA
SKING
116 00000018 ; void OSStartHigh
Rdy(void)
117 00000018 ;
118 00000018 ; Note(s) : 1) OSStartHighRdy() MUST:
119 00000018 ; a) Call OSTaskSwHook() then,
120 00000018 ; b) Set OSRunning to TRUE,
121 00000018 ; c) Switch to the highest priority task.
122 00000018 ;*******************************************************
**************************************************
123 00000018 IF (ASM_KEILRV > 0)
124 00000018 PRESERVE8
125 00000018
ARM Macro Assembler Page 4
126 00000018 AREA |.text|, CODE, READONLY
127 00000018 ARM
128 00000018 ELSE
131 ENDIF
132 00000018
133 00000018 OSStartHighRdy
134 00000018
135 00000018 IF (OS_TASK_SW_HOOK >= 1)
139 ENDIF
140 00000018
141 00000018 E321F0DF MSR CPSR_c, #(I_BIT | F_BIT | ARM_M
ODE_SYS)
; Switch to SYS mod
e with IRQ and FIQ
disabled
142 0000001C
143 0000001C E59F40B0 LDR R4, OS_Running
; OSRunning = TRUE
144 00000020 E3A05001 MOV R5, #1
145 00000024 E5C45000 STRB R5, [R4]
146 00000028
147 00000028 ; SWITCH TO HIGHEST PRIORITY TASK
148 00000028 E59F40AC LDR R4, OS_TCBHighRdy ; Get high
est priority task T
CB address
149 0000002C E5946000 LDR R6, [R4] ; get stack poin
ter
150 00000030
151 00000030 ;-------------------------------------------------------
--------------------------
152 00000030 ; LDR SP, [R6] ; switch to
the new stack
153 00000030
154 00000030 ; LDR R4, [SP], #4 ; pop new ta
sk's CPSR
155 00000030 ; MSR CPSR_cxsf, R4 ; has CPSR only
at SYS mode
156 00000030 ; LDMFD SP!, {R0-R12,LR,PC} ; pop new ta
sk's context
157 00000030 ;-------------------------------------------------------
--------------------------
158 00000030 EA000010 B OSCtxSw2
159 00000034
160 00000034 ;*******************************************************
**************************************************
161 00000034 ; PERFORM A CONTEXT SWITCH (From
task level) - OSCtxSw()
162 00000034 ;
163 00000034 ; Note(s) : 1) OSCtxSw() is called in SYS mode with BOTH
FIQ and IRQ interrupts DISABLED
164 00000034 ;
165 00000034 ; 2) The pseudo-code for OSCtxSw() is:
166 00000034 ; a) Save the current task's context onto t
he current task's stack
167 00000034 ; b) OSTCBCur->OSTCBStkPtr = SP;
168 00000034 ; c) OSTaskSwHook();
169 00000034 ; d) OSPrioCur = OSPrioHighRdy;
170 00000034 ; e) OSTCBCur = OSTCBHighRdy;
ARM Macro Assembler Page 5
171 00000034 ; f) SP = OSTCBHighRdy->
OSTCBStkPtr;
172 00000034 ; g) Restore the new task's context from th
e new task's stack
173 00000034 ; h) Return to new task's code
174 00000034 ;
175 00000034 ; 3) Upon entry:
176 00000034 ; OSTCBCur points to the OS_TCB of the
task to suspend
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