📄 os_cpu_a.lst
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154
155 /* EEPROM Data Register */
156 #define EEDR _SFR_IO8(0x1D)
157
158 /* EEPROM Address Register */
159 #define EEAR _SFR_IO16(0x1E)
160 #define EEARL _SFR_IO8(0x1E)
161 #define EEARH _SFR_IO8(0x1F)
162
163 /* EEPROM Control Register */
164 #define EERIE 3
165 #define EEMWE 2
166 #define EEWE 1
167 #define EERE 0
168
169 #endif /* __COMPILING_AVR_LIBC__ */
170
171 #if defined (__AVR_AT94K__)
172 # include <avr/ioat94k.h>
173 #elif defined (__AVR_AT43USB320__)
174 # include <avr/io43u32x.h>
175 #elif defined (__AVR_AT43USB355__)
176 # include <avr/io43u35x.h>
177 #elif defined (__AVR_AT76C711__)
178 # include <avr/io76c711.h>
179 #elif defined (__AVR_AT86RF401__)
180 # include <avr/io86r401.h>
181 #elif defined (__AVR_AT90PWM2__)
182 # include <avr/io90pwmx.h>
183 #elif defined (__AVR_AT90PWM3__)
184 # include <avr/io90pwmx.h>
185 #elif defined (__AVR_ATmega128__)
186 # include <avr/iom128.h>
1 /* Copyright (c) 2002, Peter Jansen
2 All rights reserved.
3
4 Redistribution and use in source and binary forms, with or without
5 modification, are permitted provided that the following conditions are met:
6
7 * Redistributions of source code must retain the above copyright
8 notice, this list of conditions and the following disclaimer.
9
10 * Redistributions in binary form must reproduce the above copyright
11 notice, this list of conditions and the following disclaimer in
12 the documentation and/or other materials provided with the
13 distribution.
14
15 * Neither the name of the copyright holders nor the names of
16 contributors may be used to endorse or promote products derived
17 from this software without specific prior written permission.
18
19 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 POSSIBILITY OF SUCH DAMAGE. */
30
31 /* $Id: iom128.h,v 1.18 2005/10/30 22:11:23 joerg_wunsch Exp $ */
32
33 /* avr/iom128.h - defines for ATmega128
34
35 As of 2002-08-27:
36 - This should be up to date with data sheet 2467E-AVR-05/02 */
37
38 #ifndef _AVR_IOM128_H_
39 #define _AVR_IOM128_H_ 1
40
41 /* This file should only be included from <avr/io.h>, never directly. */
42
43 #ifndef _AVR_IO_H_
44 # error "Include <avr/io.h> instead of this file."
45 #endif
46
47 #ifndef _AVR_IOXXX_H_
48 # define _AVR_IOXXX_H_ "iom128.h"
49 #else
50 # error "Attempt to include more than one <avr/ioXXX.h> file."
51 #endif
52
53 /* I/O registers */
54
55 /* Input Pins, Port F */
56 #define PINF _SFR_IO8(0x00)
57
58 /* Input Pins, Port E */
59 #define PINE _SFR_IO8(0x01)
60
61 /* Data Direction Register, Port E */
62 #define DDRE _SFR_IO8(0x02)
63
64 /* Data Register, Port E */
65 #define PORTE _SFR_IO8(0x03)
66
67 /* ADC Data Register */
68 #define ADCW _SFR_IO16(0x04) /* for backwards compatibility */
69 #ifndef __ASSEMBLER__
70 #define ADC _SFR_IO16(0x04)
71 #endif
72 #define ADCL _SFR_IO8(0x04)
73 #define ADCH _SFR_IO8(0x05)
74
75 /* ADC Control and status register */
76 #define ADCSR _SFR_IO8(0x06)
77 #define ADCSRA _SFR_IO8(0x06) /* new name in datasheet (2467E-AVR-05/02) */
78
79 /* ADC Multiplexer select */
80 #define ADMUX _SFR_IO8(0x07)
81
82 /* Analog Comparator Control and Status Register */
83 #define ACSR _SFR_IO8(0x08)
84
85 /* USART0 Baud Rate Register Low */
86 #define UBRR0L _SFR_IO8(0x09)
87
88 /* USART0 Control and Status Register B */
89 #define UCSR0B _SFR_IO8(0x0A)
90
91 /* USART0 Control and Status Register A */
92 #define UCSR0A _SFR_IO8(0x0B)
93
94 /* USART0 I/O Data Register */
95 #define UDR0 _SFR_IO8(0x0C)
96
97 /* SPI Control Register */
98 #define SPCR _SFR_IO8(0x0D)
99
100 /* SPI Status Register */
101 #define SPSR _SFR_IO8(0x0E)
102
103 /* SPI I/O Data Register */
104 #define SPDR _SFR_IO8(0x0F)
105
106 /* Input Pins, Port D */
107 #define PIND _SFR_IO8(0x10)
108
109 /* Data Direction Register, Port D */
110 #define DDRD _SFR_IO8(0x11)
111
112 /* Data Register, Port D */
113 #define PORTD _SFR_IO8(0x12)
114
115 /* Input Pins, Port C */
116 #define PINC _SFR_IO8(0x13)
117
118 /* Data Direction Register, Port C */
119 #define DDRC _SFR_IO8(0x14)
120
121 /* Data Register, Port C */
122 #define PORTC _SFR_IO8(0x15)
123
124 /* Input Pins, Port B */
125 #define PINB _SFR_IO8(0x16)
126
127 /* Data Direction Register, Port B */
128 #define DDRB _SFR_IO8(0x17)
129
130 /* Data Register, Port B */
131 #define PORTB _SFR_IO8(0x18)
132
133 /* Input Pins, Port A */
134 #define PINA _SFR_IO8(0x19)
135
136 /* Data Direction Register, Port A */
137 #define DDRA _SFR_IO8(0x1A)
138
139 /* Data Register, Port A */
140 #define PORTA _SFR_IO8(0x1B)
141
142 /* EEPROM Control Register */
143 #define EECR _SFR_IO8(0x1C)
144
145 /* EEPROM Data Register */
146 #define EEDR _SFR_IO8(0x1D)
147
148 /* EEPROM Address Register */
149 #define EEAR _SFR_IO16(0x1E)
150 #define EEARL _SFR_IO8(0x1E)
151 #define EEARH _SFR_IO8(0x1F)
152
153 /* Special Function I/O Register */
154 #define SFIOR _SFR_IO8(0x20)
155
156 /* Watchdog Timer Control Register */
157 #define WDTCR _SFR_IO8(0x21)
158
159 /* On-chip Debug Register */
160 #define OCDR _SFR_IO8(0x22)
161
162 /* Timer2 Output Compare Register */
163 #define OCR2 _SFR_IO8(0x23)
164
165 /* Timer/Counter 2 */
166 #define TCNT2 _SFR_IO8(0x24)
167
168 /* Timer/Counter 2 Control register */
169 #define TCCR2 _SFR_IO8(0x25)
170
171 /* T/C 1 Input Capture Register */
172 #define ICR1 _SFR_IO16(0x26)
173 #define ICR1L _SFR_IO8(0x26)
174 #define ICR1H _SFR_IO8(0x27)
175
176 /* Timer/Counter1 Output Compare Register B */
177 #define OCR1B _SFR_IO16(0x28)
178 #define OCR1BL _SFR_IO8(0x28)
179 #define OCR1BH _SFR_IO8(0x29)
180
181 /* Timer/Counter1 Output Compare Register A */
182 #define OCR1A _SFR_IO16(0x2A)
183 #define OCR1AL _SFR_IO8(0x2A)
184 #define OCR1AH _SFR_IO8(0x2B)
185
186 /* Timer/Counter 1 */
187 #define TCNT1 _SFR_IO16(0x2C)
187 #elif defined (__AVR_ATmega1280__)
188 # include <avr/iom1280.h>
189 #elif defined (__AVR_ATmega1281__)
190 # include <avr/iom1281.h>
191 #elif defined (__AVR_AT90CAN32__)
192 # include <avr/iocan32.h>
193 #elif defined (__AVR_AT90CAN64__)
194 # include <avr/iocan64.h>
195 #elif defined (__AVR_AT90CAN128__)
196 # include <avr/iocan128.h>
197 #elif defined (__AVR_AT90USB646__)
198 # include <avr/iousb646.h>
199 #elif defined (__AVR_AT90USB647__)
200 # include <avr/iousb647.h>
201 #elif defined (__AVR_AT90USB1286__)
202 # include <avr/iousb1286.h>
203 #elif defined (__AVR_AT90USB1287__)
204 # include <avr/iousb1287.h>
205 #elif defined (__AVR_ATmega64__)
206 # include <avr/iom64.h>
207 #elif defined (__AVR_ATmega640__)
208 # include <avr/iom640.h>
209 #elif defined (__AVR_ATmega644__)
210 # include <avr/iom644.h>
211 #elif defined (__AVR_ATmega644P__)
212 # include <avr/iom644.h>
213 #elif defined (__AVR_ATmega645__)
214 # include <avr/iom645.h>
215 #elif defined (__AVR_ATmega6450__)
216 # include <avr/iom6450.h>
217 #elif defined (__AVR_ATmega649__)
218 # include <avr/iom649.h>
219 #elif defined (__AVR_ATmega6490__)
220 # include <avr/iom6490.h>
221 #elif defined (__AVR_ATmega103__)
222 # include <avr/iom103.h>
223 #elif defined (__AVR_ATmega32__)
224 # include <avr/iom32.h>
225 #elif defined (__AVR_ATmega323__)
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