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}
BlockParameterDefaults {
Block {
BlockType Abs
SaturateOnIntegerOverflow on
ZeroCross on
SampleTime "-1"
}
Block {
BlockType Constant
Value "1"
VectorParams1D on
SamplingMode "Sample based"
OutDataTypeMode "Inherit from 'Constant value'"
OutDataType "sfix(16)"
ConRadixGroup "Use specified scaling"
OutScaling "2^0"
SampleTime "inf"
FramePeriod "inf"
}
Block {
BlockType Demux
Outputs "4"
DisplayOption "none"
BusSelectionMode off
}
Block {
BlockType FrameConversion
OutFrame "Frame based"
}
Block {
BlockType Fcn
Expr "sin(u[1])"
SampleTime "-1"
}
Block {
BlockType Gain
Gain "1"
Multiplication "Element-wise(K.*u)"
ParameterDataTypeMode "Same as input"
ParameterDataType "sfix(16)"
ParameterScalingMode "Best Precision: Matrix-wise"
ParameterScaling "2^0"
OutDataTypeMode "Same as input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
SampleTime "-1"
}
Block {
BlockType Ground
}
Block {
BlockType InitialCondition
Value "1"
SampleTime "-1"
}
Block {
BlockType Inport
Port "1"
UseBusObject off
BusObject "BusObject"
BusOutputAsStruct off
PortDimensions "-1"
SampleTime "-1"
DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
LatchByDelayingOutsideSignal off
LatchByCopyingInsideSignal off
Interpolate on
}
Block {
BlockType Integrator
ExternalReset "none"
InitialConditionSource "internal"
InitialCondition "0"
LimitOutput off
UpperSaturationLimit "inf"
LowerSaturationLimit "-inf"
ShowSaturationPort off
ShowStatePort off
AbsoluteTolerance "auto"
IgnoreLimit off
ZeroCross on
ContinuousStateAttributes "''"
}
Block {
BlockType Math
Operator "exp"
OutputSignalType "auto"
SampleTime "-1"
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
}
Block {
BlockType Outport
Port "1"
UseBusObject off
BusObject "BusObject"
BusOutputAsStruct off
PortDimensions "-1"
SampleTime "-1"
DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
OutputWhenDisabled "held"
InitialOutput "[]"
}
Block {
BlockType Product
Inputs "2"
Multiplication "Element-wise(.*)"
CollapseMode "All dimensions"
CollapseDim "1"
InputSameDT on
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Zero"
SaturateOnIntegerOverflow on
SampleTime "-1"
}
Block {
BlockType RelationalOperator
Operator ">="
InputSameDT on
LogicOutDataTypeMode "Logical (see Configuration Parameters: Optimiza"
"tion)"
LogicDataType "uint(8)"
ZeroCross on
SampleTime "-1"
}
Block {
BlockType Reshape
OutputDimensionality "1-D array"
OutputDimensions "[1,1]"
}
Block {
BlockType Scope
ModelBased off
TickLabels "OneTimeTick"
ZoomMode "on"
Grid "on"
TimeRange "auto"
YMin "-5"
YMax "5"
SaveToWorkspace off
SaveName "ScopeData"
LimitDataPoints on
MaxDataPoints "5000"
Decimation "1"
SampleInput off
SampleTime "-1"
}
Block {
BlockType "S-Function"
FunctionName "system"
SFunctionModules "''"
PortCounts "[]"
}
Block {
BlockType SignalSpecification
Dimensions "-1"
SampleTime "-1"
DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
}
Block {
BlockType Sin
SineType "Time based"
TimeSource "Use simulation time"
Amplitude "1"
Bias "0"
Frequency "1"
Phase "0"
Samples "10"
Offset "0"
SampleTime "-1"
VectorParams1D on
}
Block {
BlockType StateSpace
A "1"
B "1"
C "1"
D "1"
X0 "0"
AbsoluteTolerance "auto"
ContinuousStateAttributes "''"
Realization "auto"
}
Block {
BlockType SubSystem
ShowPortLabels "FromPortIcon"
Permissions "ReadWrite"
PermitHierarchicalResolution "All"
TreatAsAtomicUnit off
SystemSampleTime "-1"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
SimViewingDevice off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
}
Block {
BlockType Sum
IconShape "rectangular"
Inputs "++"
CollapseMode "All dimensions"
CollapseDim "1"
InputSameDT on
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
SampleTime "-1"
}
Block {
BlockType Terminator
}
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Arial"
FontSize 10
FontWeight "normal"
FontAngle "normal"
UseDisplayTextAsClickCallback off
}
LineDefaults {
FontName "Arial"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "qpsk"
Location [2, 82, 1014, 721]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
ReportName "simulink-default.rpt"
Block {
BlockType Reference
Name "Analog\nFilter Design1"
Ports [1, 1]
Position [510, 40, 570, 70]
SourceBlock "dsparch4/Analog\nFilter Design"
SourceType "Analog Filter Design"
method "Butterworth"
filttype "Lowpass"
N "3"
Wlo "pi"
Whi "80"
Rp "2"
Rs "40"
}
Block {
BlockType Reference
Name "Analog\nFilter Design2"
Ports [1, 1]
Position [510, 110, 570, 140]
SourceBlock "dsparch4/Analog\nFilter Design"
SourceType "Analog Filter Design"
method "Butterworth"
filttype "Lowpass"
N "3"
Wlo "pi"
Whi "80"
Rp "2"
Rs "40"
}
Block {
BlockType Reference
Name "Analog\nFilter Design3"
Ports [1, 1]
Position [510, 280, 570, 310]
SourceBlock "dsparch4/Analog\nFilter Design"
SourceType "Analog Filter Design"
method "Butterworth"
filttype "Lowpass"
N "3"
Wlo "pi"
Whi "80"
Rp "2"
Rs "40"
}
Block {
BlockType Reference
Name "Analog\nFilter Design4"
Ports [1, 1]
Position [510, 350, 570, 380]
SourceBlock "dsparch4/Analog\nFilter Design"
SourceType "Analog Filter Design"
method "Butterworth"
filttype "Lowpass"
N "3"
Wlo "pi"
Whi "80"
Rp "2"
Rs "40"
}
Block {
BlockType Reference
Name "Compare\nTo Zero"
Ports [1, 1]
Position [495, 440, 525, 470]
Orientation "left"
NamePlacement "alternate"
SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo "
"Zero"
SourceType "Compare To Zero"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
relop ">="
LogicOutDataTypeMode "uint8"
ZeroCross off
}
Block {
BlockType Reference
Name "Compare\nTo Zero1"
Ports [1, 1]
Position [495, 545, 525, 575]
Orientation "left"
NamePlacement "alternate"
SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo "
"Zero"
SourceType "Compare To Zero"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
relop ">="
LogicOutDataTypeMode "uint8"
ZeroCross off
}
Block {
BlockType Gain
Name "Gain"
Position [805, 440, 835, 470]
Orientation "left"
NamePlacement "alternate"
Gain "2"
ParameterDataTypeMode "Inherit via internal rule"
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Gain
Name "Gain1"
Position [805, 545, 835, 575]
Orientation "left"
NamePlacement "alternate"
Gain "2"
ParameterDataTypeMode "Inherit via internal rule"
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType SubSystem
Name "PLL"
Ports [4, 4]
Position [675, 182, 715, 243]
Orientation "left"
BackgroundColor "yellow"
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
FunctionWithSeparateData off
MaskHideContents off
System {
Name "PLL"
Location [2, 78, 1022, 717]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Block {
BlockType Inport
Name "In1"
Position [485, 123, 515, 137]
Orientation "left"
IconDisplay "Port number"
}
Block {
BlockType Inport
Name "In2"
Position [485, 133, 515, 147]
Orientation "left"
Port "2"
IconDisplay "Port number"
}
Block {
BlockType Inport
Name "In3"
Position [485, 143, 515, 157]
Orientation "left"
Port "3"
IconDisplay "Port number"
}
Block {
BlockType Inport
Name "In4"
Position [485, 153, 515, 167]
Orientation "left"
Port "4"
IconDisplay "Port number"
}
Block {
BlockType Reference
Name "Analog\nFilter Design5"
Ports [1, 1]
Position [300, 117, 365, 173]
Orientation "left"
NamePlacement "alternate"
SourceBlock "dsparch4/Analog\nFilter Design"
SourceType "Analog Filter Design"
method "Butterworth"
filttype "Lowpass"
N "3"
Wlo "3*pi"
Whi "80"
Rp "2"
Rs "40"
}
Block {
BlockType Reference
Name "Continuous-Time\nVCO"
Ports [1, 1]
Position [80, 30, 155, 60]
Orientation "left"
NamePlacement "alternate"
SourceBlock "commsynccomp2/Continuous-Time\nVCO"
SourceType "Continuous-Time VCO"
ShowPortLabels "FromPortIcon"
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