lock_19.vhd

来自「对saa7113缓存的逻辑控制单元实现」· VHDL 代码 · 共 18 行

library ieee;
use ieee.std_logic_1164.all;
entity lock_19 is
  port(
         addr_in: in std_logic_vector(18 downto 0);
         lock: in std_logic;
         addr_out : out std_logic_vector(18 downto 0));
end entity;
architecture one of lock_19 is 
 begin
   process(lock,addr_in)
    begin
      if lock='1' then 
         addr_out<=addr_in;
       
      end if;
end process;
end one;