div2.vhd

来自「对saa7113缓存的逻辑控制单元实现」· VHDL 代码 · 共 18 行

library ieee;
use ieee.std_logic_1164.all;
entity div2 is
port(
    clk:in std_logic;
    clk_div2: out std_logic);
end entity;
architecture one of div2 is 
 begin
   process(clk)
     variable q :std_logic;    
    begin
      if rising_edge(clk)then
           q:= not(q);
      end if;
    clk_div2<=q;
end process;
end one;