clkscan2.tan.qmsg

来自「采用Quartus2编写的数码管扫描显示电路 共有三个电路 电路1：当按下启」· QMSG 代码 · 共 11 行 · 第 1/3 页

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clkdiv1ms:inst3\|clkout " "Info: Detected ripple clock \"clkdiv1ms:inst3\|clkout\" as buffer" {  } { { "clkdiv1ms.v" "" { Text "e:/clk_scan/clkscan2/clkdiv1ms.v" 4 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkdiv1ms:inst3\|clkout" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "button:inst4\|signal " "Info: Detected ripple clock \"button:inst4\|signal\" as buffer" {  } { { "button.v" "" { Text "e:/clk_scan/clkscan2/button.v" 4 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "button:inst4\|signal" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "clkdiv:inst\|clkout " "Info: Detected ripple clock \"clkdiv:inst\|clkout\" as buffer" {  } { { "clkdiv.v" "" { Text "e:/clk_scan/clkscan2/clkdiv.v" 4 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkdiv:inst\|clkout" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register clkscan:inst6\|enable register clkscan:inst6\|data\[2\] 126.2 MHz 7.924 ns Internal " "Info: Clock \"clk\" has Internal fmax of 126.2 MHz between source register \"clkscan:inst6\|enable\" and destination register \"clkscan:inst6\|data\[2\]\" (period= 7.924 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.161 ns + Longest register register " "Info: + Longest register to register delay is 2.161 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clkscan:inst6\|enable 1 REG LC_X51_Y21_N7 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X51_Y21_N7; Fanout = 12; REG Node = 'clkscan:inst6\|enable'" {  } { { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "" { clkscan:inst6|enable } "NODE_NAME" } "" } } { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.543 ns) + CELL(0.292 ns) 0.835 ns clkscan:inst6\|data\[2\]~112 2 COMB LC_X51_Y21_N2 1 " "Info: 2: + IC(0.543 ns) + CELL(0.292 ns) = 0.835 ns; Loc. = LC_X51_Y21_N2; Fanout = 1; COMB Node = 'clkscan:inst6\|data\[2\]~112'" {  } { { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "0.835 ns" { clkscan:inst6|enable clkscan:inst6|data[2]~112 } "NODE_NAME" } "" } } { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.459 ns) + CELL(0.867 ns) 2.161 ns clkscan:inst6\|data\[2\] 3 REG LC_X51_Y21_N3 10 " "Info: 3: + IC(0.459 ns) + CELL(0.867 ns) = 2.161 ns; Loc. = LC_X51_Y21_N3; Fanout = 10; REG Node = 'clkscan:inst6\|data\[2\]'" {  } { { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "1.326 ns" { clkscan:inst6|data[2]~112 clkscan:inst6|data[2] } "NODE_NAME" } "" } } { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.159 ns 53.63 % " "Info: Total cell delay = 1.159 ns ( 53.63 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.002 ns 46.37 % " "Info: Total interconnect delay = 1.002 ns ( 46.37 % )" {  } {  } 0}  } { { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "2.161 ns" { clkscan:inst6|enable clkscan:inst6|data[2]~112 clkscan:inst6|data[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.161 ns" { clkscan:inst6|enable clkscan:inst6|data[2]~112 clkscan:inst6|data[2] } { 0.000ns 0.543ns 0.459ns } { 0.000ns 0.292ns 0.867ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-5.502 ns - Smallest " "Info: - Smallest clock skew is -5.502 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.729 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 7.729 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 40 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 40; CLK Node = 'clk'" {  } { { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "" { clk } "NODE_NAME" } "" } } { "clkscan2.bdf" "" { Schematic "e:/clk_scan/clkscan2/clkscan2.bdf" { { 24 -8 160 40 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(0.935 ns) 3.434 ns clkdiv:inst\|clkout 2 REG LC_X8_Y13_N1 12 " "Info: 2: + IC(1.030 ns) + CELL(0.935 ns) = 3.434 ns; Loc. = LC_X8_Y13_N1; Fanout = 12; REG Node = 'clkdiv:inst\|clkout'" {  } { { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "1.965 ns" { clk clkdiv:inst|clkout } "NODE_NAME" } "" } } { "clkdiv.v" "" { Text "e:/clk_scan/clkscan2/clkdiv.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.584 ns) + CELL(0.711 ns) 7.729 ns clkscan:inst6\|data\[2\] 3 REG LC_X51_Y21_N3 10 " "Info: 3: + IC(3.584 ns) + CELL(0.711 ns) = 7.729 ns; Loc. = LC_X51_Y21_N3; Fanout = 10; REG Node = 'clkscan:inst6\|data\[2\]'" {  } { { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "4.295 ns" { clkdiv:inst|clkout clkscan:inst6|data[2] } "NODE_NAME" } "" } } { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 40.30 % " "Info: Total cell delay = 3.115 ns ( 40.30 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.614 ns 59.70 % " "Info: Total interconnect delay = 4.614 ns ( 59.70 % )" {  } {  } 0}  } { { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "7.729 ns" { clk clkdiv:inst|clkout clkscan:inst6|data[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.729 ns" { clk clk~out0 clkdiv:inst|clkout clkscan:inst6|data[2] } { 0.000ns 0.000ns 1.030ns 3.584ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 13.231 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 13.231 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 40 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 40; CLK Node = 'clk'" {  } { { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "" { clk } "NODE_NAME" } "" } } { "clkscan2.bdf" "" { Schematic "e:/clk_scan/clkscan2/clkscan2.bdf" { { 24 -8 160 40 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.990 ns) + CELL(0.935 ns) 3.394 ns clkdiv1ms:inst3\|clkout 2 REG LC_X7_Y12_N2 16 " "Info: 2: + IC(0.990 ns) + CELL(0.935 ns) = 3.394 ns; Loc. = LC_X7_Y12_N2; Fanout = 16; REG Node = 'clkdiv1ms:inst3\|clkout'" {  } { { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "1.925 ns" { clk clkdiv1ms:inst3|clkout } "NODE_NAME" } "" } } { "clkdiv1ms.v" "" { Text "e:/clk_scan/clkscan2/clkdiv1ms.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.087 ns) + CELL(0.935 ns) 8.416 ns button:inst4\|signal 3 REG LC_X8_Y11_N0 14 " "Info: 3: + IC(4.087 ns) + CELL(0.935 ns) = 8.416 ns; Loc. = LC_X8_Y11_N0; Fanout = 14; REG Node = 'button:inst4\|signal'" {  } { { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "5.022 ns" { clkdiv1ms:inst3|clkout button:inst4|signal } "NODE_NAME" } "" } } { "button.v" "" { Text "e:/clk_scan/clkscan2/button.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.104 ns) + CELL(0.711 ns) 13.231 ns clkscan:inst6\|enable 4 REG LC_X51_Y21_N7 12 " "Info: 4: + IC(4.104 ns) + CELL(0.711 ns) = 13.231 ns; Loc. = LC_X51_Y21_N7; Fanout = 12; REG Node = 'clkscan:inst6\|enable'" {  } { { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "4.815 ns" { button:inst4|signal clkscan:inst6|enable } "NODE_NAME" } "" } } { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.050 ns 30.61 % " "Info: Total cell delay = 4.050 ns ( 30.61 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.181 ns 69.39 % " "Info: Total interconnect delay = 9.181 ns ( 69.39 % )" {  } {  } 0}  } { { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "13.231 ns" { clk clkdiv1ms:inst3|clkout button:inst4|signal clkscan:inst6|enable } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "13.231 ns" { clk clk~out0 clkdiv1ms:inst3|clkout button:inst4|signal clkscan:inst6|enable } { 0.000ns 0.000ns 0.990ns 4.087ns 4.104ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0}  } { { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "7.729 ns" { clk clkdiv:inst|clkout clkscan:inst6|data[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.729 ns" { clk clk~out0 clkdiv:inst|clkout clkscan:inst6|data[2] } { 0.000ns 0.000ns 1.030ns 3.584ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "13.231 ns" { clk clkdiv1ms:inst3|clkout button:inst4|signal clkscan:inst6|enable } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "13.231 ns" { clk clk~out0 clkdiv1ms:inst3|clkout button:inst4|signal clkscan:inst6|enable } { 0.000ns 0.000ns 0.990ns 4.087ns 4.104ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 18 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 14 -1 0 } }  } 0}  } { { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "2.161 ns" { clkscan:inst6|enable clkscan:inst6|data[2]~112 clkscan:inst6|data[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.161 ns" { clkscan:inst6|enable clkscan:inst6|data[2]~112 clkscan:inst6|data[2] } { 0.000ns 0.543ns 0.459ns } { 0.000ns 0.292ns 0.867ns } } } { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "7.729 ns" { clk clkdiv:inst|clkout clkscan:inst6|data[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.729 ns" { clk clk~out0 clkdiv:inst|clkout clkscan:inst6|data[2] } { 0.000ns 0.000ns 1.030ns 3.584ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "13.231 ns" { clk clkdiv1ms:inst3|clkout button:inst4|signal clkscan:inst6|enable } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "13.231 ns" { clk clk~out0 clkdiv1ms:inst3|clkout button:inst4|signal clkscan:inst6|enable } { 0.000ns 0.000ns 0.990ns 4.087ns 4.104ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "button:inst4\|signal reset clk 8.495 ns register " "Info: tsu for register \"button:inst4\|signal\" (data pin = \"reset\", clock pin = \"clk\") is 8.495 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "16.650 ns + Longest pin register " "Info: + Longest pin to register delay is 16.650 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns reset 1 PIN PIN_128 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_128; Fanout = 1; PIN Node = 'reset'" {  } { { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "" { reset } "NODE_NAME" } "" } } { "clkscan2.bdf" "" { Schematic "e:/clk_scan/clkscan2/clkscan2.bdf" { { 352 -8 160 368 "reset" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(9.298 ns) + CELL(0.114 ns) 10.881 ns button:inst4\|always0~0 2 COMB LC_X9_Y11_N9 3 " "Info: 2: + IC(9.298 ns) + CELL(0.114 ns) = 10.881 ns; Loc. = LC_X9_Y11_N9; Fanout = 3; COMB Node = 'button:inst4\|always0~0'" {  } { { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "9.412 ns" { reset button:inst4|always0~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.683 ns) + CELL(0.423 ns) 11.987 ns button:inst4\|add~435 3 COMB LC_X8_Y11_N1 2 " "Info: 3: + IC(0.683 ns) + CELL(0.423 ns) = 11.987 ns; Loc. = LC_X8_Y11_N1; Fanout = 2; COMB Node = 'button:inst4\|add~435'" {  } { { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "1.106 ns" { button:inst4|always0~0 button:inst4|add~435 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 12.065 ns button:inst4\|add~423 4 COMB LC_X8_Y11_N2 2 " "Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 12.065 ns; Loc. = LC_X8_Y11_N2; Fanout = 2; COMB Node = 'button:inst4\|add~423'" {  } { { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "0.078 ns" { button:inst4|add~435 button:inst4|add~423 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 12.143 ns button:inst4\|add~429 5 COMB LC_X8_Y11_N3 2 " "Info: 5: + IC(0.000 ns) + CELL(0.078 ns) = 12.143 ns; Loc. = LC_X8_Y11_N3; Fanout = 2; COMB Node = 'button:inst4\|add~429'" {  } { { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "0.078 ns" { button:inst4|add~423 button:inst4|add~429 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 12.321 ns button:inst4\|add~459 6 COMB LC_X8_Y11_N4 3 " "Info: 6: + IC(0.000 ns) + CELL(0.178 ns) = 12.321 ns; Loc. = LC_X8_Y11_N4; Fanout = 3; COMB Node = 'button:inst4\|add~459'" {  } { { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "0.178 ns" { button:inst4|add~429 button:inst4|add~459 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.621 ns) 12.942 ns button:inst4\|add~445 7 COMB LC_X8_Y11_N5 2 " "Info: 7: + IC(0.000 ns) + CELL(0.621 ns) = 12.942 ns; Loc. = LC_X8_Y11_N5; Fanout = 2; COMB Node = 'button:inst4\|add~445'" {  } { { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "0.621 ns" { button:inst4|add~459 button:inst4|add~445 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.727 ns) + CELL(0.292 ns) 13.961 ns button:inst4\|add~450 8 COMB LC_X7_Y11_N7 1 " "Info: 8: + IC(0.727 ns) + CELL(0.292 ns) = 13.961 ns; Loc. = LC_X7_Y11_N7; Fanout = 1; COMB Node = 'button:inst4\|add~450'" {  } { { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "1.019 ns" { button:inst4|add~445 button:inst4|add~450 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.951 ns) + CELL(0.738 ns) 16.650 ns button:inst4\|signal 9 REG LC_X8_Y11_N0 14 " "Info: 9: + IC(1.951 ns) + CELL(0.738 ns) = 16.650 ns; Loc. = LC_X8_Y11_N0; Fanout = 14; REG Node = 'button:inst4\|signal'" {  } { { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "2.689 ns" { button:inst4|add~450 button:inst4|signal } "NODE_NAME" } "" } } { "button.v" "" { Text "e:/clk_scan/clkscan2/button.v" 4 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.991 ns 23.97 % " "Info: Total cell delay = 3.991 ns ( 23.97 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "12.659 ns 76.03 % " "Info: Total interconnect delay = 12.659 ns ( 76.03 % )" {  } {  } 0}  } { { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "16.650 ns" { reset button:inst4|always0~0 button:inst4|add~435 button:inst4|add~423 button:inst4|add~429 button:inst4|add~459 button:inst4|add~445 button:inst4|add~450 button:inst4|signal } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "16.650 ns" { reset reset~out0 button:inst4|always0~0 button:inst4|add~435 button:inst4|add~423 button:inst4|add~429 button:inst4|add~459 button:inst4|add~445 button:inst4|add~450 button:inst4|signal } { 0.000ns 0.000ns 9.298ns 0.683ns 0.000ns 0.000ns 0.000ns 0.000ns 0.727ns 1.951ns } { 0.000ns 1.469ns 0.114ns 0.423ns 0.078ns 0.078ns 0.178ns 0.621ns 0.292ns 0.738ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "button.v" "" { Text "e:/clk_scan/clkscan2/button.v" 4 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.192 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 8.192 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 40 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 40; CLK Node = 'clk'" {  } { { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "" { clk } "NODE_NAME" } "" } } { "clkscan2.bdf" "" { Schematic "e:/clk_scan/clkscan2/clkscan2.bdf" { { 24 -8 160 40 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.990 ns) + CELL(0.935 ns) 3.394 ns clkdiv1ms:inst3\|clkout 2 REG LC_X7_Y12_N2 16 " "Info: 2: + IC(0.990 ns) + CELL(0.935 ns) = 3.394 ns; Loc. = LC_X7_Y12_N2; Fanout = 16; REG Node = 'clkdiv1ms:inst3\|clkout'" {  } { { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "1.925 ns" { clk clkdiv1ms:inst3|clkout } "NODE_NAME" } "" } } { "clkdiv1ms.v" "" { Text "e:/clk_scan/clkscan2/clkdiv1ms.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.087 ns) + CELL(0.711 ns) 8.192 ns button:inst4\|signal 3 REG LC_X8_Y11_N0 14 " "Info: 3: + IC(4.087 ns) + CELL(0.711 ns) = 8.192 ns; Loc. = LC_X8_Y11_N0; Fanout = 14; REG Node = 'button:inst4\|signal'" {  } { { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "4.798 ns" { clkdiv1ms:inst3|clkout button:inst4|signal } "NODE_NAME" } "" } } { "button.v" "" { Text "e:/clk_scan/clkscan2/button.v" 4 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 38.02 % " "Info: Total cell delay = 3.115 ns ( 38.02 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.077 ns 61.98 % " "Info: Total interconnect delay = 5.077 ns ( 61.98 % )" {  } {  } 0}  } { { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "8.192 ns" { clk clkdiv1ms:inst3|clkout button:inst4|signal } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.192 ns" { clk clk~out0 clkdiv1ms:inst3|clkout button:inst4|signal } { 0.000ns 0.000ns 0.990ns 4.087ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0}  } { { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "16.650 ns" { reset button:inst4|always0~0 button:inst4|add~435 button:inst4|add~423 button:inst4|add~429 button:inst4|add~459 button:inst4|add~445 button:inst4|add~450 button:inst4|signal } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "16.650 ns" { reset reset~out0 button:inst4|always0~0 button:inst4|add~435 button:inst4|add~423 button:inst4|add~429 button:inst4|add~459 button:inst4|add~445 button:inst4|add~450 button:inst4|signal } { 0.000ns 0.000ns 9.298ns 0.683ns 0.000ns 0.000ns 0.000ns 0.000ns 0.727ns 1.951ns } { 0.000ns 1.469ns 0.114ns 0.423ns 0.078ns 0.078ns 0.178ns 0.621ns 0.292ns 0.738ns } } } { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "8.192 ns" { clk clkdiv1ms:inst3|clkout button:inst4|signal } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.192 ns" { clk clk~out0 clkdiv1ms:inst3|clkout button:inst4|signal } { 0.000ns 0.000ns 0.990ns 4.087ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk out\[0\] clkscan:inst6\|data\[1\] 13.409 ns register " "Info: tco from clock \"clk\" to destination pin \"out\[0\]\" through register \"clkscan:inst6\|data\[1\]\" is 13.409 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.729 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 7.729 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 40 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 40; CLK Node = 'clk'" {  } { { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "" { clk } "NODE_NAME" } "" } } { "clkscan2.bdf" "" { Schematic "e:/clk_scan/clkscan2/clkscan2.bdf" { { 24 -8 160 40 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(0.935 ns) 3.434 ns clkdiv:inst\|clkout 2 REG LC_X8_Y13_N1 12 " "Info: 2: + IC(1.030 ns) + CELL(0.935 ns) = 3.434 ns; Loc. = LC_X8_Y13_N1; Fanout = 12; REG Node = 'clkdiv:inst\|clkout'" {  } { { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "1.965 ns" { clk clkdiv:inst|clkout } "NODE_NAME" } "" } } { "clkdiv.v" "" { Text "e:/clk_scan/clkscan2/clkdiv.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.584 ns) + CELL(0.711 ns) 7.729 ns clkscan:inst6\|data\[1\] 3 REG LC_X52_Y21_N2 10 " "Info: 3: + IC(3.584 ns) + CELL(0.711 ns) = 7.729 ns; Loc. = LC_X52_Y21_N2; Fanout = 10; REG Node = 'clkscan:inst6\|data\[1\]'" {  } { { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "4.295 ns" { clkdiv:inst|clkout clkscan:inst6|data[1] } "NODE_NAME" } "" } } { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 40.30 % " "Info: Total cell delay = 3.115 ns ( 40.30 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.614 ns 59.70 % " "Info: Total interconnect delay = 4.614 ns ( 59.70 % )" {  } {  } 0}  } { { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "7.729 ns" { clk clkdiv:inst|clkout clkscan:inst6|data[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.729 ns" { clk clk~out0 clkdiv:inst|clkout clkscan:inst6|data[1] } { 0.000ns 0.000ns 1.030ns 3.584ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 14 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.456 ns + Longest register pin " "Info: + Longest register to pin delay is 5.456 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clkscan:inst6\|data\[1\] 1 REG LC_X52_Y21_N2 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X52_Y21_N2; Fanout = 10; REG Node = 'clkscan:inst6\|data\[1\]'" {  } { { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "" { clkscan:inst6|data[1] } "NODE_NAME" } "" } } { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.946 ns) + CELL(0.590 ns) 1.536 ns p7segment:inst7\|reduce_or~49 2 COMB LC_X51_Y21_N5 1 " "Info: 2: + IC(0.946 ns) + CELL(0.590 ns) = 1.536 ns; Loc. = LC_X51_Y21_N5; Fanout = 1; COMB Node = 'p7segment:inst7\|reduce_or~49'" {  } { { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "1.536 ns" { clkscan:inst6|data[1] p7segment:inst7|reduce_or~49 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.796 ns) + CELL(2.124 ns) 5.456 ns out\[0\] 3 PIN PIN_173 0 " "Info: 3: + IC(1.796 ns) + CELL(2.124 ns) = 5.456 ns; Loc. = PIN_173; Fanout = 0; PIN Node = 'out\[0\]'" {  } { { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "3.920 ns" { p7segment:inst7|reduce_or~49 out[0] } "NODE_NAME" } "" } } { "clkscan2.bdf" "" { Schematic "e:/clk_scan/clkscan2/clkscan2.bdf" { { 296 432 608 312 "out\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.714 ns 49.74 % " "Info: Total cell delay = 2.714 ns ( 49.74 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.742 ns 50.26 % " "Info: Total interconnect delay = 2.742 ns ( 50.26 % )" {  } {  } 0}  } { { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "5.456 ns" { clkscan:inst6|data[1] p7segment:inst7|reduce_or~49 out[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.456 ns" { clkscan:inst6|data[1] p7segment:inst7|reduce_or~49 out[0] } { 0.000ns 0.946ns 1.796ns } { 0.000ns 0.590ns 2.124ns } } }  } 0}  } { { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "7.729 ns" { clk clkdiv:inst|clkout clkscan:inst6|data[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.729 ns" { clk clk~out0 clkdiv:inst|clkout clkscan:inst6|data[1] } { 0.000ns 0.000ns 1.030ns 3.584ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "5.456 ns" { clkscan:inst6|data[1] p7segment:inst7|reduce_or~49 out[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.456 ns" { clkscan:inst6|data[1] p7segment:inst7|reduce_or~49 out[0] } { 0.000ns 0.946ns 1.796ns } { 0.000ns 0.590ns 2.124ns } } }  } 0}