clkscan2.fit.qmsg

来自「采用Quartus2编写的数码管扫描显示电路 共有三个电路 电路1：当按下启」· QMSG 代码 · 共 40 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 14 21:22:49 2008 " "Info: Processing started: Mon Apr 14 21:22:49 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off clkscan2 -c clkscan2 " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off clkscan2 -c clkscan2" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "clkscan2 EP1C12Q240C8 " "Info: Selected device EP1C12Q240C8 for design \"clkscan2\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C6Q240C8 " "Info: Device EP1C6Q240C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN 28 " "Info: Automatically promoted signal \"clk\" to use Global clock in PIN 28" {  } { { "clkscan2.bdf" "" { Schematic "e:/clk_scan/clkscan2/clkscan2.bdf" { { 24 -8 160 40 "clk" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clkdiv1ms:inst3\|clkout Global clock " "Info: Automatically promoted signal \"clkdiv1ms:inst3\|clkout\" to use Global clock" {  } { { "clkdiv1ms.v" "" { Text "e:/clk_scan/clkscan2/clkdiv1ms.v" 4 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clkdiv:inst\|clkout Global clock " "Info: Automatically promoted signal \"clkdiv:inst\|clkout\" to use Global clock" {  } { { "clkdiv.v" "" { Text "e:/clk_scan/clkscan2/clkdiv.v" 4 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "button:inst4\|signal Global clock " "Info: Automatically promoted some destinations of signal \"button:inst4\|signal\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "button:inst4\|always0~0 " "Info: Destination \"button:inst4\|always0~0\" may be non-global or may not use global clock" {  } {  } 0}  } { { "button.v" "" { Text "e:/clk_scan/clkscan2/button.v" 4 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "2.043 ns register register " "Info: Estimated most critical path is register to register delay of 2.043 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clkscan:inst6\|enable 1 REG LAB_X51_Y21 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X51_Y21; Fanout = 12; REG Node = 'clkscan:inst6\|enable'" {  } { { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "" { clkscan:inst6|enable } "NODE_NAME" } "" } } { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.626 ns) + CELL(0.114 ns) 0.740 ns clkscan:inst6\|data\[2\]~112 2 COMB LAB_X51_Y21 1 " "Info: 2: + IC(0.626 ns) + CELL(0.114 ns) = 0.740 ns; Loc. = LAB_X51_Y21; Fanout = 1; COMB Node = 'clkscan:inst6\|data\[2\]~112'" {  } { { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "0.740 ns" { clkscan:inst6|enable clkscan:inst6|data[2]~112 } "NODE_NAME" } "" } } { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.436 ns) + CELL(0.867 ns) 2.043 ns clkscan:inst6\|data\[2\] 3 REG LAB_X51_Y21 10 " "Info: 3: + IC(0.436 ns) + CELL(0.867 ns) = 2.043 ns; Loc. = LAB_X51_Y21; Fanout = 10; REG Node = 'clkscan:inst6\|data\[2\]'" {  } { { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "1.303 ns" { clkscan:inst6|data[2]~112 clkscan:inst6|data[2] } "NODE_NAME" } "" } } { "clkscan.v" "" { Text "e:/clk_scan/clkscan2/clkscan.v" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.981 ns 48.02 % " "Info: Total cell delay = 0.981 ns ( 48.02 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.062 ns 51.98 % " "Info: Total interconnect delay = 1.062 ns ( 51.98 % )" {  } {  } 0}  } { { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "2.043 ns" { clkscan:inst6|enable clkscan:inst6|data[2]~112 clkscan:inst6|data[2] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "1 " "Warning: The following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "out\[7\] GND " "Info: Pin out\[7\] has GND driving its datain port" {  } { { "clkscan2.bdf" "" { Schematic "e:/clk_scan/clkscan2/clkscan2.bdf" { { 296 432 608 312 "out\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "out\[7\]" } } } } { "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" "" { Report "e:/clk_scan/clkscan2/db/clkscan2_cmp.qrpt" Compiler "clkscan2" "UNKNOWN" "V1" "e:/clk_scan/clkscan2/db/clkscan2.quartus_db" { Floorplan "e:/clk_scan/clkscan2/" "" "" { out[7] } "NODE_NAME" } "" } } { "e:/clk_scan/clkscan2/clkscan2.fld" "" { Floorplan "e:/clk_scan/clkscan2/clkscan2.fld" "" "" { out[7] } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 14 21:22:56 2008 " "Info: Processing ended: Mon Apr 14 21:22:56 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0}  } {  } 0}