clkscan.v

来自「采用Quartus2编写的数码管扫描显示电路 共有三个电路 电路1：当按下启」· Verilog 代码 · 共 64 行

//s8~s1为state的8个状态，分别用于控制scan_en[8:1]
`define s1 3'd0 
 `define s2 3'd1
 `define s3 3'd2
 `define s4 3'd3
 `define s5 3'd4
 `define s6 3'd5
 `define s7 3'd6
 `define s8 3'd7

module clkscan(clk, start, reset, scan_en, data);
input clk, start, reset;
output[8:1] scan_en;
output[3:0] data;
reg[8:1] scan_en;
reg[3:0] data;
reg[2:0] state;
reg enable;

//---- 下面的always模块产生enable信号
  always @(negedge start or negedge reset)
	begin
		if(!start)enable = 1;
		else 
				enable = 0;
	end
	
// ---- 下面的always模块进行计数 
always @(negedge clk or negedge reset )
    begin
      if(!reset)        //① 异步复位（注意复位时使数码管1一直点亮）
		begin
			state = `s1;
			scan_en='b00000001;
			data = 0;
		end
	  else if(enable)     //② 若按下startn按钮
// 则进行状态机的状态转移
// 并产生串行扫描使能信号
		begin
			case(state)
			`s1:begin state = `s2;scan_en='b00000010;end
			`s2:begin state = `s3;scan_en='b00000100;end
			`s3:begin state = `s4;scan_en='b00001000;end
			`s4:begin state = `s5;scan_en='b00010000;end
			`s5:begin state = `s6;scan_en='b00100000;end
			`s6:begin state = `s7;scan_en='b01000000;end
			`s7:begin state = `s8;scan_en='b10000000;end
			`s8:begin state = `s1;scan_en='b00000001;end
			default:begin state = `s1;scan_en='b00000001;end
			endcase
// 扫描数据计数器加1计数
			if(data==9)
				data = 0;
			else 
				data = data+1;
		end
      else  begin state = `s1;scan_en='b00000001;end  //③ 当resetn无效、enable为0时，state返回初始状态
    end
	
endmodule