clkscan2.map.rpt

来自「采用Quartus2编写的数码管扫描显示电路 共有三个电路 电路1：当按下启」· RPT 代码 · 共 309 行 · 第 1/2 页

; |clkscan2                  ; 164 (0)     ; 69           ; 0           ; 19   ; 0            ; 95 (0)       ; 41 (0)            ; 28 (0)           ; 52 (0)          ; |clkscan2                 ;
;    |button:inst2|          ; 26 (26)     ; 8            ; 0           ; 0    ; 0            ; 18 (18)      ; 7 (7)             ; 1 (1)            ; 7 (7)           ; |clkscan2|button:inst2    ;
;    |button:inst4|          ; 26 (26)     ; 8            ; 0           ; 0    ; 0            ; 18 (18)      ; 7 (7)             ; 1 (1)            ; 7 (7)           ; |clkscan2|button:inst4    ;
;    |clkdiv1ms:inst3|       ; 36 (36)     ; 16           ; 0           ; 0    ; 0            ; 20 (20)      ; 10 (10)           ; 6 (6)            ; 15 (15)         ; |clkscan2|clkdiv1ms:inst3 ;
;    |clkdiv:inst|           ; 55 (55)     ; 24           ; 0           ; 0    ; 0            ; 31 (31)      ; 15 (15)           ; 9 (9)            ; 23 (23)         ; |clkscan2|clkdiv:inst     ;
;    |clkscan:inst6|         ; 14 (14)     ; 13           ; 0           ; 0    ; 0            ; 1 (1)        ; 2 (2)             ; 11 (11)          ; 0 (0)           ; |clkscan2|clkscan:inst6   ;
;    |p7segment:inst7|       ; 7 (7)       ; 0            ; 0           ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |clkscan2|p7segment:inst7 ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+-----------------------------------------------------------------------------------------------------------+
; State Machine - |clkscan2|clkscan:inst6|state                                                             ;
+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+
; Name      ; state.111 ; state.001 ; state.010 ; state.011 ; state.100 ; state.101 ; state.110 ; state.000 ;
+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+
; state.000 ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ;
; state.110 ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 1         ; 1         ;
; state.101 ; 0         ; 0         ; 0         ; 0         ; 0         ; 1         ; 0         ; 1         ;
; state.100 ; 0         ; 0         ; 0         ; 0         ; 1         ; 0         ; 0         ; 1         ;
; state.011 ; 0         ; 0         ; 0         ; 1         ; 0         ; 0         ; 0         ; 1         ;
; state.010 ; 0         ; 0         ; 1         ; 0         ; 0         ; 0         ; 0         ; 1         ;
; state.001 ; 0         ; 1         ; 0         ; 0         ; 0         ; 0         ; 0         ; 1         ;
; state.111 ; 1         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 1         ;
+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 69    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 13    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 4     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; clkscan:inst6|scan_en[1]               ; 2       ;
; clkscan:inst6|enable                   ; 12      ;
; Total number of inverted registers = 2 ;         ;
+----------------------------------------+---------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in e:/clk_scan/clkscan2/clkscan2.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Mon Apr 14 21:22:45 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clkscan2 -c clkscan2
Info: Found 1 design units, including 1 entities, in source file button.v
    Info: Found entity 1: button
Info: Found 1 design units, including 1 entities, in source file p7segment.v
    Info: Found entity 1: p7segment
Info: Found 1 design units, including 1 entities, in source file clkdiv1ms.v
    Info: Found entity 1: clkdiv1ms
Info: Found 1 design units, including 1 entities, in source file clkdiv.v
    Info: Found entity 1: clkdiv
Info: Found 1 design units, including 1 entities, in source file clkscan.v
    Info: Found entity 1: clkscan
Info: Found 1 design units, including 1 entities, in source file clkscan2.bdf
    Info: Found entity 1: clkscan2
Info: Elaborating entity "clkscan2" for the top level hierarchy
Info: Elaborating entity "p7segment" for hierarchy "p7segment:inst7"
Info: Elaborating entity "clkscan" for hierarchy "clkscan:inst6"
Warning: Verilog HDL assignment warning at clkscan.v(23): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at clkscan.v(25): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at clkscan.v(34): truncated value with size 32 to match size of target (8)
Warning: Verilog HDL assignment warning at clkscan.v(35): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clkscan.v(42): truncated value with size 32 to match size of target (8)
Warning: Verilog HDL assignment warning at clkscan.v(43): truncated value with size 32 to match size of target (8)
Warning: Verilog HDL assignment warning at clkscan.v(44): truncated value with size 32 to match size of target (8)
Warning: Verilog HDL assignment warning at clkscan.v(45): truncated value with size 32 to match size of target (8)
Warning: Verilog HDL assignment warning at clkscan.v(46): truncated value with size 32 to match size of target (8)
Warning: Verilog HDL assignment warning at clkscan.v(47): truncated value with size 32 to match size of target (8)
Warning: Verilog HDL assignment warning at clkscan.v(48): truncated value with size 32 to match size of target (8)
Warning: Verilog HDL assignment warning at clkscan.v(49): truncated value with size 32 to match size of target (8)
Warning: Verilog HDL assignment warning at clkscan.v(50): truncated value with size 32 to match size of target (8)
Warning: Verilog HDL assignment warning at clkscan.v(54): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clkscan.v(56): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clkscan.v(58): truncated value with size 32 to match size of target (8)
Info: Elaborating entity "clkdiv" for hierarchy "clkdiv:inst"
Warning: Verilog HDL assignment warning at clkdiv.v(10): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at clkdiv.v(12): truncated value with size 32 to match size of target (23)
Warning: Verilog HDL assignment warning at clkdiv.v(14): truncated value with size 32 to match size of target (23)
Info: Elaborating entity "button" for hierarchy "button:inst2"
Warning: Verilog HDL assignment warning at button.v(11): truncated value with size 32 to match size of target (7)
Warning: Verilog HDL assignment warning at button.v(13): truncated value with size 32 to match size of target (7)
Info: Elaborating entity "clkdiv1ms" for hierarchy "clkdiv1ms:inst3"
Warning: Verilog HDL assignment warning at clkdiv1ms.v(10): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at clkdiv1ms.v(12): truncated value with size 32 to match size of target (15)
Warning: Verilog HDL assignment warning at clkdiv1ms.v(14): truncated value with size 32 to match size of target (15)
Info: Duplicate registers merged to single register
    Info: Duplicate register "button:inst4|enable~reg0" merged to single register "button:inst4|signal", power-up level changed
    Info: Duplicate register "button:inst2|enable~reg0" merged to single register "button:inst2|signal", power-up level changed
Info: State machine "|clkscan2|clkscan:inst6|state" contains 8 states and 0 state bits
Info: Selected Auto state machine encoding method for state machine "|clkscan2|clkscan:inst6|state"
Info: Encoding result for state machine "|clkscan2|clkscan:inst6|state"
    Info: Completed encoding using 8 state bits
        Info: Encoded state bit "clkscan:inst6|state.111"
        Info: Encoded state bit "clkscan:inst6|state.001"
        Info: Encoded state bit "clkscan:inst6|state.010"
        Info: Encoded state bit "clkscan:inst6|state.011"
        Info: Encoded state bit "clkscan:inst6|state.100"
        Info: Encoded state bit "clkscan:inst6|state.101"
        Info: Encoded state bit "clkscan:inst6|state.110"
        Info: Encoded state bit "clkscan:inst6|state.000"
    Info: State "|clkscan2|clkscan:inst6|state.000" uses code string "00000000"
    Info: State "|clkscan2|clkscan:inst6|state.110" uses code string "00000011"
    Info: State "|clkscan2|clkscan:inst6|state.101" uses code string "00000101"
    Info: State "|clkscan2|clkscan:inst6|state.100" uses code string "00001001"
    Info: State "|clkscan2|clkscan:inst6|state.011" uses code string "00010001"
    Info: State "|clkscan2|clkscan:inst6|state.010" uses code string "00100001"
    Info: State "|clkscan2|clkscan:inst6|state.001" uses code string "01000001"
    Info: State "|clkscan2|clkscan:inst6|state.111" uses code string "10000001"
Info: Duplicate registers merged to single register
    Info: Duplicate register "clkscan:inst6|state.111" merged to single register "clkscan:inst6|scan_en[8]"
    Info: Duplicate register "clkscan:inst6|state.110" merged to single register "clkscan:inst6|scan_en[7]"
    Info: Duplicate register "clkscan:inst6|state.101" merged to single register "clkscan:inst6|scan_en[6]"
    Info: Duplicate register "clkscan:inst6|state.100" merged to single register "clkscan:inst6|scan_en[5]"
    Info: Duplicate register "clkscan:inst6|state.011" merged to single register "clkscan:inst6|scan_en[4]"
    Info: Duplicate register "clkscan:inst6|state.010" merged to single register "clkscan:inst6|scan_en[3]"
    Info: Duplicate register "clkscan:inst6|state.001" merged to single register "clkscan:inst6|scan_en[2]"
    Info: Duplicate register "clkscan:inst6|state.000" merged to single register "clkscan:inst6|scan_en[1]", power-up level changed
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "out[7]" stuck at GND
Info: Registers with preset signals will power-up high
Info: Implemented 183 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 16 output pins
    Info: Implemented 164 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 26 warnings
    Info: Processing ended: Mon Apr 14 21:22:48 2008
    Info: Elapsed time: 00:00:03