clkscan1.map.qmsg

来自「采用Quartus2编写的数码管扫描显示电路 共有三个电路 电路1：当按下启」· QMSG 代码 · 共 32 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 14 20:57:18 2008 " "Info: Processing started: Mon Apr 14 20:57:18 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off clkscan1 -c clkscan1 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clkscan1 -c clkscan1" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clkdiv.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file clkdiv.v" { { "Info" "ISGN_ENTITY_NAME" "1 clkdiv " "Info: Found entity 1: clkdiv" {  } { { "clkdiv.v" "" { Text "e:/实验四 数码管扫描显示电路/clkscan1/clkdiv.v" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clkscan1.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file clkscan1.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 clkscan1 " "Info: Found entity 1: clkscan1" {  } { { "clkscan1.bdf" "" { Schematic "e:/实验四 数码管扫描显示电路/clkscan1/clkscan1.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "p7segment.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file p7segment.v" { { "Info" "ISGN_ENTITY_NAME" "1 p7segment " "Info: Found entity 1: p7segment" {  } { { "p7segment.v" "" { Text "e:/实验四 数码管扫描显示电路/clkscan1/p7segment.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "button.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file button.v" { { "Info" "ISGN_ENTITY_NAME" "1 button " "Info: Found entity 1: button" {  } { { "button.v" "" { Text "e:/实验四 数码管扫描显示电路/clkscan1/button.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "e:/实验四 数码管扫描显示电路/clkscan1/clkscan1.v " "Warning: Can't analyze file -- file e:/实验四 数码管扫描显示电路/clkscan1/clkscan1.v is missing" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clkscan.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file clkscan.v" { { "Info" "ISGN_ENTITY_NAME" "1 clkscan " "Info: Found entity 1: clkscan" {  } { { "clkscan.v" "" { Text "e:/实验四 数码管扫描显示电路/clkscan1/clkscan.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "clkscan1 " "Info: Elaborating entity \"clkscan1\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "p7segment p7segment:inst6 " "Info: Elaborating entity \"p7segment\" for hierarchy \"p7segment:inst6\"" {  } { { "clkscan1.bdf" "inst6" { Schematic "e:/实验四 数码管扫描显示电路/clkscan1/clkscan1.bdf" { { 112 760 912 208 "inst6" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clkscan clkscan:inst5 " "Info: Elaborating entity \"clkscan\" for hierarchy \"clkscan:inst5\"" {  } { { "clkscan1.bdf" "inst5" { Schematic "e:/实验四 数码管扫描显示电路/clkscan1/clkscan1.bdf" { { 96 512 672 192 "inst5" "" } } } }  } 0}
{ "Warning" "WVRFX_VERI_NO_DFF_INFERRED" "clkscan.v(12) " "Warning: Verilog HDL warning at clkscan.v(12): can't infer register for Procedural Assignment in Always Construct because the clock signal isn't obvious. Generated combinational logic instead." {  } { { "clkscan.v" "" { Text "e:/实验四 数码管扫描显示电路/clkscan1/clkscan.v" 12 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "8 1 clkscan.v(13) " "Warning: Verilog HDL assignment warning at clkscan.v(13): truncated value with size 8 to match size of target (1)" {  } { { "clkscan.v" "" { Text "e:/实验四 数码管扫描显示电路/clkscan1/clkscan.v" 13 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 clkscan.v(15) " "Warning: Verilog HDL assignment warning at clkscan.v(15): truncated value with size 32 to match size of target (1)" {  } { { "clkscan.v" "" { Text "e:/实验四 数码管扫描显示电路/clkscan1/clkscan.v" 15 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clkscan.v(21) " "Warning: Verilog HDL assignment warning at clkscan.v(21): truncated value with size 32 to match size of target (4)" {  } { { "clkscan.v" "" { Text "e:/实验四 数码管扫描显示电路/clkscan1/clkscan.v" 21 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clkscan.v(26) " "Warning: Verilog HDL assignment warning at clkscan.v(26): truncated value with size 32 to match size of target (4)" {  } { { "clkscan.v" "" { Text "e:/实验四 数码管扫描显示电路/clkscan1/clkscan.v" 26 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clkscan.v(27) " "Warning: Verilog HDL assignment warning at clkscan.v(27): truncated value with size 32 to match size of target (4)" {  } { { "clkscan.v" "" { Text "e:/实验四 数码管扫描显示电路/clkscan1/clkscan.v" 27 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clkscan.v(30) " "Warning: Verilog HDL assignment warning at clkscan.v(30): truncated value with size 32 to match size of target (4)" {  } { { "clkscan.v" "" { Text "e:/实验四 数码管扫描显示电路/clkscan1/clkscan.v" 30 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clkdiv clkdiv:inst " "Info: Elaborating entity \"clkdiv\" for hierarchy \"clkdiv:inst\"" {  } { { "clkscan1.bdf" "inst" { Schematic "e:/实验四 数码管扫描显示电路/clkscan1/clkscan1.bdf" { { 96 288 408 192 "inst" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "button button:inst3 " "Info: Elaborating entity \"button\" for hierarchy \"button:inst3\"" {  } { { "clkscan1.bdf" "inst3" { Schematic "e:/实验四 数码管扫描显示电路/clkscan1/clkscan1.bdf" { { 224 296 408 320 "inst3" "" } } } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 button.v(17) " "Warning: Verilog HDL assignment warning at button.v(17): truncated value with size 32 to match size of target (1)" {  } { { "button.v" "" { Text "e:/实验四 数码管扫描显示电路/clkscan1/button.v" 17 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 button.v(18) " "Warning: Verilog HDL assignment warning at button.v(18): truncated value with size 32 to match size of target (1)" {  } { { "button.v" "" { Text "e:/实验四 数码管扫描显示电路/clkscan1/button.v" 18 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 button.v(22) " "Warning: Verilog HDL assignment warning at button.v(22): truncated value with size 32 to match size of target (1)" {  } { { "button.v" "" { Text "e:/实验四 数码管扫描显示电路/clkscan1/button.v" 22 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 button.v(23) " "Warning: Verilog HDL assignment warning at button.v(23): truncated value with size 32 to match size of target (1)" {  } { { "button.v" "" { Text "e:/实验四 数码管扫描显示电路/clkscan1/button.v" 23 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 button.v(28) " "Warning: Verilog HDL assignment warning at button.v(28): truncated value with size 32 to match size of target (7)" {  } { { "button.v" "" { Text "e:/实验四 数码管扫描显示电路/clkscan1/button.v" 28 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 button.v(30) " "Warning: Verilog HDL assignment warning at button.v(30): truncated value with size 32 to match size of target (7)" {  } { { "button.v" "" { Text "e:/实验四 数码管扫描显示电路/clkscan1/button.v" 30 0 0 } }  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "out\[7\] GND " "Warning: Pin \"out\[7\]\" stuck at GND" {  } { { "clkscan1.bdf" "" { Schematic "e:/实验四 数码管扫描显示电路/clkscan1/clkscan1.bdf" { { 136 944 1120 152 "out\[7..0\]" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "scan_en\[8\] VCC " "Warning: Pin \"scan_en\[8\]\" stuck at VCC" {  } { { "clkscan1.bdf" "" { Schematic "e:/实验四 数码管扫描显示电路/clkscan1/clkscan1.bdf" { { 56 776 952 72 "scan_en\[8..1\]" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "scan_en\[7\] VCC " "Warning: Pin \"scan_en\[7\]\" stuck at VCC" {  } { { "clkscan1.bdf" "" { Schematic "e:/实验四 数码管扫描显示电路/clkscan1/clkscan1.bdf" { { 56 776 952 72 "scan_en\[8..1\]" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "scan_en\[6\] VCC " "Warning: Pin \"scan_en\[6\]\" stuck at VCC" {  } { { "clkscan1.bdf" "" { Schematic "e:/实验四 数码管扫描显示电路/clkscan1/clkscan1.bdf" { { 56 776 952 72 "scan_en\[8..1\]" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "scan_en\[5\] VCC " "Warning: Pin \"scan_en\[5\]\" stuck at VCC" {  } { { "clkscan1.bdf" "" { Schematic "e:/实验四 数码管扫描显示电路/clkscan1/clkscan1.bdf" { { 56 776 952 72 "scan_en\[8..1\]" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "scan_en\[4\] VCC " "Warning: Pin \"scan_en\[4\]\" stuck at VCC" {  } { { "clkscan1.bdf" "" { Schematic "e:/实验四 数码管扫描显示电路/clkscan1/clkscan1.bdf" { { 56 776 952 72 "scan_en\[8..1\]" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "scan_en\[3\] VCC " "Warning: Pin \"scan_en\[3\]\" stuck at VCC" {  } { { "clkscan1.bdf" "" { Schematic "e:/实验四 数码管扫描显示电路/clkscan1/clkscan1.bdf" { { 56 776 952 72 "scan_en\[8..1\]" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "scan_en\[2\] VCC " "Warning: Pin \"scan_en\[2\]\" stuck at VCC" {  } { { "clkscan1.bdf" "" { Schematic "e:/实验四 数码管扫描显示电路/clkscan1/clkscan1.bdf" { { 56 776 952 72 "scan_en\[8..1\]" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "scan_en\[1\] VCC " "Warning: Pin \"scan_en\[1\]\" stuck at VCC" {  } { { "clkscan1.bdf" "" { Schematic "e:/实验四 数码管扫描显示电路/clkscan1/clkscan1.bdf" { { 56 776 952 72 "scan_en\[8..1\]" "" } } } }  } 0}  } {  } 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "clkscan.v" "" { Text "e:/实验四 数码管扫描显示电路/clkscan1/clkscan.v" 7 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "134 " "Info: Implemented 134 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "20 " "Info: Implemented 20 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "111 " "Info: Implemented 111 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 24 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 24 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 14 20:57:19 2008 " "Info: Processing ended: Mon Apr 14 20:57:19 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}