clkdiv.v

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module clkdiv(clkin, clk_4Hz, clk_1KHz);
input clkin;
output clk_4Hz, clk_1KHz;
	
	reg [14:0] counter1;
	reg [7:0]  counter2;
	reg	clk_4Hz, clk_1KHz;
	always@(posedge clkin)
	begin
		
		 if(counter1==15'd19999)
			begin
			counter1<=15'd0;
			clk_1KHz<=1'd1;
			
				if(counter2 == 8'd250)
					begin
					counter2<=8'd0;
					clk_4Hz<=1'd1;
					end
				else
					begin
					counter2<=counter2+1'b1;
					clk_4Hz<=1'd0;
					end
			
			end
		else
			begin
			counter1<=counter1+1'b1;
			clk_1KHz<=1'd0;
			end
	end

endmodule

/*
     
//将输入时钟20MHz分频为1000Hz，20000分频
module clkdiv(clkin, clkout);
	input	clkin;
	output	clkout;
	reg		clkout;				 
	reg[14:0]	count;//2^15
	
	always @(posedge clkin)		
		begin
			clkout <= (count == 20000) ? 1 : 0;	
				if (count == 20000)
					count <= 0;
				else
					count <= count + 1;
		end
endmodule

*/