clkscan1.map.rpt

采用Quartus2编写的数码管扫描显示电路 共有三个电路 电路1：当按下启动计时按钮时

; Total logic elements              ; 111     ;
; Total combinational functions     ; 88      ;
;     -- Total 4-input functions    ; 26      ;
;     -- Total 3-input functions    ; 2       ;
;     -- Total 2-input functions    ; 22      ;
;     -- Total 1-input functions    ; 37      ;
;     -- Total 0-input functions    ; 1       ;
; Combinational cells for routing   ; 0       ;
; Total registers                   ; 46      ;
; Total logic cells in carry chains ; 37      ;
; I/O pins                          ; 23      ;
; Maximum fan-out node              ; clk     ;
; Maximum fan-out                   ; 25      ;
; Total fan-out                     ; 332     ;
; Average fan-out                   ; 2.48    ;
+-----------------------------------+---------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                             ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name       ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------------+
; |clkscan1                  ; 111 (0)     ; 46           ; 0           ; 23   ; 0            ; 65 (0)       ; 23 (0)            ; 23 (0)           ; 37 (0)          ; |clkscan1                 ;
;    |button:inst3|          ; 20 (20)     ; 8            ; 0           ; 0    ; 0            ; 12 (12)      ; 5 (5)             ; 3 (3)            ; 7 (7)           ; |clkscan1|button:inst3    ;
;    |button:inst4|          ; 20 (20)     ; 8            ; 0           ; 0    ; 0            ; 12 (12)      ; 5 (5)             ; 3 (3)            ; 7 (7)           ; |clkscan1|button:inst4    ;
;    |clkdiv:inst|           ; 56 (56)     ; 25           ; 0           ; 0    ; 0            ; 31 (31)      ; 13 (13)           ; 12 (12)          ; 23 (23)         ; |clkscan1|clkdiv:inst     ;
;    |clkscan:inst5|         ; 8 (8)       ; 5            ; 0           ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 5 (5)            ; 0 (0)           ; |clkscan1|clkscan:inst5   ;
;    |p7segment:inst6|       ; 7 (7)       ; 0            ; 0           ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |clkscan1|p7segment:inst6 ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 46    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 5     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 23    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; clkscan:inst5|enable                   ; 2       ;
; Total number of inverted registers = 1 ;         ;
+----------------------------------------+---------+


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                     ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------+
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |clkscan1|clkscan:inst5|scan_data[0] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in e:/实验四 数码管扫描显示电路/clkscan1/clkscan1.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Mon Apr 14 20:57:18 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clkscan1 -c clkscan1
Info: Found 1 design units, including 1 entities, in source file clkdiv.v
    Info: Found entity 1: clkdiv
Info: Found 1 design units, including 1 entities, in source file clkscan1.bdf
    Info: Found entity 1: clkscan1
Info: Found 1 design units, including 1 entities, in source file p7segment.v
    Info: Found entity 1: p7segment
Info: Found 1 design units, including 1 entities, in source file button.v
    Info: Found entity 1: button
Warning: Can't analyze file -- file e:/实验四 数码管扫描显示电路/clkscan1/clkscan1.v is missing
Info: Found 1 design units, including 1 entities, in source file clkscan.v
    Info: Found entity 1: clkscan
Info: Elaborating entity "clkscan1" for the top level hierarchy
Info: Elaborating entity "p7segment" for hierarchy "p7segment:inst6"
Info: Elaborating entity "clkscan" for hierarchy "clkscan:inst5"
Warning: Verilog HDL warning at clkscan.v(12): can't infer register for Procedural Assignment in Always Construct because the clock signal isn't obvious. Generated combinational logic instead.
Warning: Verilog HDL assignment warning at clkscan.v(13): truncated value with size 8 to match size of target (1)
Warning: Verilog HDL assignment warning at clkscan.v(15): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at clkscan.v(21): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clkscan.v(26): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clkscan.v(27): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clkscan.v(30): truncated value with size 32 to match size of target (4)
Info: Elaborating entity "clkdiv" for hierarchy "clkdiv:inst"
Info: Elaborating entity "button" for hierarchy "button:inst3"
Warning: Verilog HDL assignment warning at button.v(17): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at button.v(18): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at button.v(22): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at button.v(23): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at button.v(28): truncated value with size 32 to match size of target (7)
Warning: Verilog HDL assignment warning at button.v(30): truncated value with size 32 to match size of target (7)
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "out[7]" stuck at GND
    Warning: Pin "scan_en[8]" stuck at VCC
    Warning: Pin "scan_en[7]" stuck at VCC
    Warning: Pin "scan_en[6]" stuck at VCC
    Warning: Pin "scan_en[5]" stuck at VCC
    Warning: Pin "scan_en[4]" stuck at VCC
    Warning: Pin "scan_en[3]" stuck at VCC
    Warning: Pin "scan_en[2]" stuck at VCC
    Warning: Pin "scan_en[1]" stuck at VCC
Info: Registers with preset signals will power-up high
Info: Implemented 134 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 20 output pins
    Info: Implemented 111 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 24 warnings
    Info: Processing ended: Mon Apr 14 20:57:19 2008
    Info: Elapsed time: 00:00:02