clkscan.v

来自「采用Quartus2编写的数码管扫描显示电路 共有三个电路 电路1：当按下启」· Verilog 代码 · 共 37 行

module clkscan(clk, startn, resetn, scan_en, scan_data);
input clk, startn, resetn;
output[8:1] scan_en;
output[3:0] scan_data;
reg[8:1] scan_en;
reg[3:0] scan_data;
reg enable;

//---- 下面的always模块产生enable信号
  always @(negedge startn or negedge resetn)
	begin
		 scan_en = 8'b11111111;
		if(!startn)enable = 8'b11111111;
		else 
				enable = 0;
	end
	
// ---- 下面的always模块进行计数 
  always @(posedge clk or negedge resetn ) 
	begin
		if(!resetn)scan_data = 0;
		else
			begin
				if(enable)
					begin
						if(scan_data==9)	scan_data = 0;
						else scan_data = scan_data+1;
					end
				else
					scan_data = 0;
			end
	end
	
endmodule