clkscan3.map.qmsg

采用Quartus2编写的数码管扫描显示电路 共有三个电路 电路1：当按下启动计时按钮时

{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 timer.v(31) " "Warning: Verilog HDL assignment warning at timer.v(31): truncated value with size 32 to match size of target (8)" {  } { { "timer.v" "" { Text "e:/clk_scan/clkscan3/timer.v" 31 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 timer.v(38) " "Warning: Verilog HDL assignment warning at timer.v(38): truncated value with size 32 to match size of target (8)" {  } { { "timer.v" "" { Text "e:/clk_scan/clkscan3/timer.v" 38 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 timer.v(44) " "Warning: Verilog HDL assignment warning at timer.v(44): truncated value with size 32 to match size of target (1)" {  } { { "timer.v" "" { Text "e:/clk_scan/clkscan3/timer.v" 44 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 timer.v(45) " "Warning: Verilog HDL assignment warning at timer.v(45): truncated value with size 32 to match size of target (8)" {  } { { "timer.v" "" { Text "e:/clk_scan/clkscan3/timer.v" 45 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 timer.v(49) " "Warning: Verilog HDL assignment warning at timer.v(49): truncated value with size 32 to match size of target (1)" {  } { { "timer.v" "" { Text "e:/clk_scan/clkscan3/timer.v" 49 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 timer.v(50) " "Warning: Verilog HDL assignment warning at timer.v(50): truncated value with size 32 to match size of target (8)" {  } { { "timer.v" "" { Text "e:/clk_scan/clkscan3/timer.v" 50 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 timer.v(59) " "Warning: Verilog HDL assignment warning at timer.v(59): truncated value with size 32 to match size of target (8)" {  } { { "timer.v" "" { Text "e:/clk_scan/clkscan3/timer.v" 59 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 timer.v(65) " "Warning: Verilog HDL assignment warning at timer.v(65): truncated value with size 32 to match size of target (1)" {  } { { "timer.v" "" { Text "e:/clk_scan/clkscan3/timer.v" 65 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 timer.v(66) " "Warning: Verilog HDL assignment warning at timer.v(66): truncated value with size 32 to match size of target (8)" {  } { { "timer.v" "" { Text "e:/clk_scan/clkscan3/timer.v" 66 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 timer.v(70) " "Warning: Verilog HDL assignment warning at timer.v(70): truncated value with size 32 to match size of target (1)" {  } { { "timer.v" "" { Text "e:/clk_scan/clkscan3/timer.v" 70 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 timer.v(71) " "Warning: Verilog HDL assignment warning at timer.v(71): truncated value with size 32 to match size of target (8)" {  } { { "timer.v" "" { Text "e:/clk_scan/clkscan3/timer.v" 71 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clkdiv clkdiv:inst " "Info: Elaborating entity \"clkdiv\" for hierarchy \"clkdiv:inst\"" {  } { { "clkscan3.bdf" "inst" { Schematic "e:/clk_scan/clkscan3/clkscan3.bdf" { { -8 200 296 88 "inst" "" } } } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 clkdiv.v(10) " "Warning: Verilog HDL assignment warning at clkdiv.v(10): truncated value with size 32 to match size of target (1)" {  } { { "clkdiv.v" "" { Text "e:/clk_scan/clkscan3/clkdiv.v" 10 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 clkdiv.v(12) " "Warning: Verilog HDL assignment warning at clkdiv.v(12): truncated value with size 32 to match size of target (23)" {  } { { "clkdiv.v" "" { Text "e:/clk_scan/clkscan3/clkdiv.v" 12 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 clkdiv.v(14) " "Warning: Verilog HDL assignment warning at clkdiv.v(14): truncated value with size 32 to match size of target (23)" {  } { { "clkdiv.v" "" { Text "e:/clk_scan/clkscan3/clkdiv.v" 14 0 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "clkscan:inst7\|scan_en\[6\] data_in GND " "Warning: Reduced register \"clkscan:inst7\|scan_en\[6\]\" with stuck data_in port to stuck value GND" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan3/clkscan.v" 12 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "clkscan:inst7\|scan_en\[3\] data_in GND " "Warning: Reduced register \"clkscan:inst7\|scan_en\[3\]\" with stuck data_in port to stuck value GND" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan3/clkscan.v" 12 -1 0 } }  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "button:inst5\|enable~reg0 button:inst5\|signal " "Info: Duplicate register \"button:inst5\|enable~reg0\" merged to single register \"button:inst5\|signal\", power-up level changed" {  } { { "button.v" "" { Text "e:/clk_scan/clkscan3/button.v" 4 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "button:inst9\|enable~reg0 button:inst9\|signal " "Info: Duplicate register \"button:inst9\|enable~reg0\" merged to single register \"button:inst9\|signal\", power-up level changed" {  } { { "button.v" "" { Text "e:/clk_scan/clkscan3/button.v" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|clkscan3\|clkscan:inst7\|state 6 0 " "Info: State machine \"\|clkscan3\|clkscan:inst7\|state\" contains 6 states and 0 state bits" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan3/clkscan.v" 16 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|clkscan3\|clkscan:inst7\|state " "Info: Selected Auto state machine encoding method for state machine \"\|clkscan3\|clkscan:inst7\|state\"" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan3/clkscan.v" 16 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|clkscan3\|clkscan:inst7\|state " "Info: Encoding result for state machine \"\|clkscan3\|clkscan:inst7\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "6 " "Info: Completed encoding using 6 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "clkscan:inst7\|state.101 " "Info: Encoded state bit \"clkscan:inst7\|state.101\"" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan3/clkscan.v" 16 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "clkscan:inst7\|state.001 " "Info: Encoded state bit \"clkscan:inst7\|state.001\"" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan3/clkscan.v" 16 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "clkscan:inst7\|state.010 " "Info: Encoded state bit \"clkscan:inst7\|state.010\"" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan3/clkscan.v" 16 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "clkscan:inst7\|state.011 " "Info: Encoded state bit \"clkscan:inst7\|state.011\"" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan3/clkscan.v" 16 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "clkscan:inst7\|state.100 " "Info: Encoded state bit \"clkscan:inst7\|state.100\"" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan3/clkscan.v" 16 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "clkscan:inst7\|state.000 " "Info: Encoded state bit \"clkscan:inst7\|state.000\"" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan3/clkscan.v" 16 -1 0 } }  } 0}  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|clkscan3\|clkscan:inst7\|state.000 000000 " "Info: State \"\|clkscan3\|clkscan:inst7\|state.000\" uses code string \"000000\"" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan3/clkscan.v" 16 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|clkscan3\|clkscan:inst7\|state.100 000011 " "Info: State \"\|clkscan3\|clkscan:inst7\|state.100\" uses code string \"000011\"" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan3/clkscan.v" 16 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|clkscan3\|clkscan:inst7\|state.011 000101 " "Info: State \"\|clkscan3\|clkscan:inst7\|state.011\" uses code string \"000101\"" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan3/clkscan.v" 16 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|clkscan3\|clkscan:inst7\|state.010 001001 " "Info: State \"\|clkscan3\|clkscan:inst7\|state.010\" uses code string \"001001\"" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan3/clkscan.v" 16 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|clkscan3\|clkscan:inst7\|state.001 010001 " "Info: State \"\|clkscan3\|clkscan:inst7\|state.001\" uses code string \"010001\"" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan3/clkscan.v" 16 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|clkscan3\|clkscan:inst7\|state.101 100001 " "Info: State \"\|clkscan3\|clkscan:inst7\|state.101\" uses code string \"100001\"" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan3/clkscan.v" 16 -1 0 } }  } 0}  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan3/clkscan.v" 16 -1 0 } }  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "clkscan:inst7\|state.101 clkscan:inst7\|scan_en\[8\] " "Info: Duplicate register \"clkscan:inst7\|state.101\" merged to single register \"clkscan:inst7\|scan_en\[8\]\"" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan3/clkscan.v" 16 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "clkscan:inst7\|state.100 clkscan:inst7\|scan_en\[7\] " "Info: Duplicate register \"clkscan:inst7\|state.100\" merged to single register \"clkscan:inst7\|scan_en\[7\]\"" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan3/clkscan.v" 16 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "clkscan:inst7\|state.011 clkscan:inst7\|scan_en\[5\] " "Info: Duplicate register \"clkscan:inst7\|state.011\" merged to single register \"clkscan:inst7\|scan_en\[5\]\"" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan3/clkscan.v" 16 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "clkscan:inst7\|state.010 clkscan:inst7\|scan_en\[4\] " "Info: Duplicate register \"clkscan:inst7\|state.010\" merged to single register \"clkscan:inst7\|scan_en\[4\]\"" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan3/clkscan.v" 16 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "clkscan:inst7\|state.001 clkscan:inst7\|scan_en\[2\] " "Info: Duplicate register \"clkscan:inst7\|state.001\" merged to single register \"clkscan:inst7\|scan_en\[2\]\"" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan3/clkscan.v" 16 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "clkscan:inst7\|state.000 clkscan:inst7\|scan_en\[1\] " "Info: Duplicate register \"clkscan:inst7\|state.000\" merged to single register \"clkscan:inst7\|scan_en\[1\]\", power-up level changed" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan3/clkscan.v" 16 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/lpm_divide.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/lpm_divide.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide " "Info: Found entity 1: lpm_divide" {  } { { "lpm_divide.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_divide.tdf" 116 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_ndf.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_ndf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_ndf " "Info: Found entity 1: lpm_divide_ndf" {  } { { "db/lpm_divide_ndf.tdf" "" { Text "e:/clk_scan/clkscan3/db/lpm_divide_ndf.tdf" 24 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_mhg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_mhg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_mhg " "Info: Found entity 1: sign_div_unsign_mhg" {  } { { "db/sign_div_unsign_mhg.tdf" "" { Text "e:/clk_scan/clkscan3/db/sign_div_unsign_mhg.tdf" 26 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_hld.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_hld.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_hld " "Info: Found entity 1: alt_u_div_hld" {  } { { "db/alt_u_div_hld.tdf" "" { Text "e:/clk_scan/clkscan3/db/alt_u_div_hld.tdf" 32 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_ke8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_ke8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_ke8 " "Info: Found entity 1: add_sub_ke8" {  } { { "db/add_sub_ke8.tdf" "" { Text "e:/clk_scan/clkscan3/db/add_sub_ke8.tdf" 22 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_le8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_le8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_le8 " "Info: Found entity 1: add_sub_le8" {  } { { "db/add_sub_le8.tdf" "" { Text "e:/clk_scan/clkscan3/db/add_sub_le8.tdf" 22 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_me8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_me8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_me8 " "Info: Found entity 1: add_sub_me8" {  } { { "db/add_sub_me8.tdf" "" { Text "e:/clk_scan/clkscan3/db/add_sub_me8.tdf" 24 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_ne8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_ne8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_ne8 " "Info: Found entity 1: add_sub_ne8" {  } { { "db/add_sub_ne8.tdf" "" { Text "e:/clk_scan/clkscan3/db/add_sub_ne8.tdf" 24 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_oe8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_oe8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_oe8 " "Info: Found entity 1: add_sub_oe8" {  } { { "db/add_sub_oe8.tdf" "" { Text "e:/clk_scan/clkscan3/db/add_sub_oe8.tdf" 24 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_ma8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_ma8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_ma8 " "Info: Found entity 1: add_sub_ma8" {  } { { "db/add_sub_ma8.tdf" "" { Text "e:/clk_scan/clkscan3/db/add_sub_ma8.tdf" 24 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_klf.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_klf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_klf " "Info: Found entity 1: lpm_divide_klf" {  } { { "db/lpm_divide_klf.tdf" "" { Text "e:/clk_scan/clkscan3/db/lpm_divide_klf.tdf" 24 1 0 } }  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "out\[7\] GND " "Warning: Pin \"out\[7\]\" stuck at GND" {  } { { "clkscan3.bdf" "" { Schematic "e:/clk_scan/clkscan3/clkscan3.bdf" { { 392 536 712 408 "out\[7..0\]" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "scan_en\[6\] GND " "Warning: Pin \"scan_en\[6\]\" stuck at GND" {  } { { "clkscan3.bdf" "" { Schematic "e:/clk_scan/clkscan3/clkscan3.bdf" { { 40 728 904 56 "scan_en\[8..1\]" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "scan_en\[3\] GND " "Warning: Pin \"scan_en\[3\]\" stuck at GND" {  } { { "clkscan3.bdf" "" { Schematic "e:/clk_scan/clkscan3/clkscan3.bdf" { { 40 728 904 56 "scan_en\[8..1\]" "" } } } }  } 0}  } {  } 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan3/clkscan.v" 12 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "579 " "Info: Implemented 579 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "560 " "Info: Implemented 560 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 41 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 41 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 14 21:13:50 2008 " "Info: Processing ended: Mon Apr 14 21:13:50 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0}  } {  } 0}