clkscan3.map.qmsg

采用Quartus2编写的数码管扫描显示电路 共有三个电路 电路1：当按下启动计时按钮时

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 14 21:13:42 2008 " "Info: Processing started: Mon Apr 14 21:13:42 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off clkscan3 -c clkscan3 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clkscan3 -c clkscan3" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "button.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file button.v" { { "Info" "ISGN_ENTITY_NAME" "1 button " "Info: Found entity 1: button" {  } { { "button.v" "" { Text "e:/clk_scan/clkscan3/button.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clkdiv1ms.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file clkdiv1ms.v" { { "Info" "ISGN_ENTITY_NAME" "1 clkdiv1ms " "Info: Found entity 1: clkdiv1ms" {  } { { "clkdiv1ms.v" "" { Text "e:/clk_scan/clkscan3/clkdiv1ms.v" 2 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clkdiv.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file clkdiv.v" { { "Info" "ISGN_ENTITY_NAME" "1 clkdiv " "Info: Found entity 1: clkdiv" {  } { { "clkdiv.v" "" { Text "e:/clk_scan/clkscan3/clkdiv.v" 2 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "p7segment.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file p7segment.v" { { "Info" "ISGN_ENTITY_NAME" "1 p7segment " "Info: Found entity 1: p7segment" {  } { { "p7segment.v" "" { Text "e:/clk_scan/clkscan3/p7segment.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clkscan.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file clkscan.v" { { "Info" "ISGN_ENTITY_NAME" "1 clkscan " "Info: Found entity 1: clkscan" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan3/clkscan.v" 9 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "timer.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file timer.v" { { "Info" "ISGN_ENTITY_NAME" "1 timer " "Info: Found entity 1: timer" {  } { { "timer.v" "" { Text "e:/clk_scan/clkscan3/timer.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clkscan3.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file clkscan3.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 clkscan3 " "Info: Found entity 1: clkscan3" {  } { { "clkscan3.bdf" "" { Schematic "e:/clk_scan/clkscan3/clkscan3.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clkscan3_test.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file clkscan3_test.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 clkscan3_test " "Info: Found entity 1: clkscan3_test" {  } { { "clkscan3_test.bdf" "" { Schematic "e:/clk_scan/clkscan3/clkscan3_test.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "clkscan3 " "Info: Elaborating entity \"clkscan3\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "p7segment p7segment:inst8 " "Info: Elaborating entity \"p7segment\" for hierarchy \"p7segment:inst8\"" {  } { { "clkscan3.bdf" "inst8" { Schematic "e:/clk_scan/clkscan3/clkscan3.bdf" { { 192 536 688 288 "inst8" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clkscan clkscan:inst7 " "Info: Elaborating entity \"clkscan\" for hierarchy \"clkscan:inst7\"" {  } { { "clkscan3.bdf" "inst7" { Schematic "e:/clk_scan/clkscan3/clkscan3.bdf" { { 16 512 696 144 "inst7" "" } } } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 clkscan.v(23) " "Warning: Verilog HDL assignment warning at clkscan.v(23): truncated value with size 32 to match size of target (8)" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan3/clkscan.v" 23 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clkscan.v(24) " "Warning: Verilog HDL assignment warning at clkscan.v(24): truncated value with size 32 to match size of target (4)" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan3/clkscan.v" 24 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 clkscan.v(31) " "Warning: Verilog HDL assignment warning at clkscan.v(31): truncated value with size 32 to match size of target (8)" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan3/clkscan.v" 31 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 clkscan.v(32) " "Warning: Verilog HDL assignment warning at clkscan.v(32): truncated value with size 32 to match size of target (8)" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan3/clkscan.v" 32 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 clkscan.v(33) " "Warning: Verilog HDL assignment warning at clkscan.v(33): truncated value with size 32 to match size of target (8)" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan3/clkscan.v" 33 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 clkscan.v(34) " "Warning: Verilog HDL assignment warning at clkscan.v(34): truncated value with size 32 to match size of target (8)" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan3/clkscan.v" 34 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 clkscan.v(35) " "Warning: Verilog HDL assignment warning at clkscan.v(35): truncated value with size 32 to match size of target (8)" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan3/clkscan.v" 35 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 clkscan.v(36) " "Warning: Verilog HDL assignment warning at clkscan.v(36): truncated value with size 32 to match size of target (8)" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan3/clkscan.v" 36 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 clkscan.v(37) " "Warning: Verilog HDL assignment warning at clkscan.v(37): truncated value with size 32 to match size of target (8)" {  } { { "clkscan.v" "" { Text "e:/clk_scan/clkscan3/clkscan.v" 37 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clkdiv1ms clkdiv1ms:inst1 " "Info: Elaborating entity \"clkdiv1ms\" for hierarchy \"clkdiv1ms:inst1\"" {  } { { "clkscan3.bdf" "inst1" { Schematic "e:/clk_scan/clkscan3/clkscan3.bdf" { { 104 200 296 200 "inst1" "" } } } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 clkdiv1ms.v(10) " "Warning: Verilog HDL assignment warning at clkdiv1ms.v(10): truncated value with size 32 to match size of target (1)" {  } { { "clkdiv1ms.v" "" { Text "e:/clk_scan/clkscan3/clkdiv1ms.v" 10 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 15 clkdiv1ms.v(12) " "Warning: Verilog HDL assignment warning at clkdiv1ms.v(12): truncated value with size 32 to match size of target (15)" {  } { { "clkdiv1ms.v" "" { Text "e:/clk_scan/clkscan3/clkdiv1ms.v" 12 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 15 clkdiv1ms.v(14) " "Warning: Verilog HDL assignment warning at clkdiv1ms.v(14): truncated value with size 32 to match size of target (15)" {  } { { "clkdiv1ms.v" "" { Text "e:/clk_scan/clkscan3/clkdiv1ms.v" 14 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "button button:inst9 " "Info: Elaborating entity \"button\" for hierarchy \"button:inst9\"" {  } { { "clkscan3.bdf" "inst9" { Schematic "e:/clk_scan/clkscan3/clkscan3.bdf" { { 216 216 328 312 "inst9" "" } } } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 button.v(11) " "Warning: Verilog HDL assignment warning at button.v(11): truncated value with size 32 to match size of target (7)" {  } { { "button.v" "" { Text "e:/clk_scan/clkscan3/button.v" 11 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 button.v(13) " "Warning: Verilog HDL assignment warning at button.v(13): truncated value with size 32 to match size of target (7)" {  } { { "button.v" "" { Text "e:/clk_scan/clkscan3/button.v" 13 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "timer timer:inst6 " "Info: Elaborating entity \"timer\" for hierarchy \"timer:inst6\"" {  } { { "clkscan3.bdf" "inst6" { Schematic "e:/clk_scan/clkscan3/clkscan3.bdf" { { 48 352 480 176 "inst6" "" } } } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 timer.v(11) " "Warning: Verilog HDL assignment warning at timer.v(11): truncated value with size 32 to match size of target (1)" {  } { { "timer.v" "" { Text "e:/clk_scan/clkscan3/timer.v" 11 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 timer.v(12) " "Warning: Verilog HDL assignment warning at timer.v(12): truncated value with size 32 to match size of target (1)" {  } { { "timer.v" "" { Text "e:/clk_scan/clkscan3/timer.v" 12 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 timer.v(17) " "Warning: Verilog HDL assignment warning at timer.v(17): truncated value with size 32 to match size of target (8)" {  } { { "timer.v" "" { Text "e:/clk_scan/clkscan3/timer.v" 17 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 timer.v(22) " "Warning: Verilog HDL assignment warning at timer.v(22): truncated value with size 32 to match size of target (1)" {  } { { "timer.v" "" { Text "e:/clk_scan/clkscan3/timer.v" 22 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 timer.v(23) " "Warning: Verilog HDL assignment warning at timer.v(23): truncated value with size 32 to match size of target (8)" {  } { { "timer.v" "" { Text "e:/clk_scan/clkscan3/timer.v" 23 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 timer.v(27) " "Warning: Verilog HDL assignment warning at timer.v(27): truncated value with size 32 to match size of target (1)" {  } { { "timer.v" "" { Text "e:/clk_scan/clkscan3/timer.v" 27 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 timer.v(28) " "Warning: Verilog HDL assignment warning at timer.v(28): truncated value with size 32 to match size of target (8)" {  } { { "timer.v" "" { Text "e:/clk_scan/clkscan3/timer.v" 28 0 0 } }  } 0}