clkscan3.tan.qmsg

来自「采用Quartus2编写的数码管扫描显示电路 共有三个电路 电路1：当按下启」· QMSG 代码 · 共 8 行 · 第 1/5 页

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 1 " "Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "button:inst9\|signal timer:inst6\|h_clk clk 322 ps " "Info: Found hold time violation between source  pin or register \"button:inst9\|signal\" and destination pin or register \"timer:inst6\|h_clk\" for clock \"clk\" (Hold time is 322 ps)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "5.680 ns + Largest " "Info: + Largest clock skew is 5.680 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 13.439 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 13.439 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 40 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 40; CLK Node = 'clk'" {  } { { "e:/clk_scan/clkscan3/db/clkscan3_cmp.qrpt" "" { Report "e:/clk_scan/clkscan3/db/clkscan3_cmp.qrpt" Compiler "clkscan3" "UNKNOWN" "V1" "e:/clk_