clkscan3.hier_info

采用Quartus2编写的数码管扫描显示电路 共有三个电路 电路1：当按下启动计时按钮时

|clkscan3
out[0] <= p7segment:inst8.out[0]
out[1] <= p7segment:inst8.out[1]
out[2] <= p7segment:inst8.out[2]
out[3] <= p7segment:inst8.out[3]
out[4] <= p7segment:inst8.out[4]
out[5] <= p7segment:inst8.out[5]
out[6] <= p7segment:inst8.out[6]
out[7] <= p7segment:inst8.out[7]
clk => clkdiv1ms:inst1.clkin
clk => clkdiv:inst.clkin
reset => button:inst9.phn
start => button:inst5.phn
scan_en[1] <= clkscan:inst7.scan_en[1]
scan_en[2] <= clkscan:inst7.scan_en[2]
scan_en[3] <= clkscan:inst7.scan_en[3]
scan_en[4] <= clkscan:inst7.scan_en[4]
scan_en[5] <= clkscan:inst7.scan_en[5]
scan_en[6] <= clkscan:inst7.scan_en[6]
scan_en[7] <= clkscan:inst7.scan_en[7]
scan_en[8] <= clkscan:inst7.scan_en[8]


|clkscan3|p7segment:inst8
out[0] <= reduce_or~6.DB_MAX_OUTPUT_PORT_TYPE
out[1] <= reduce_or~5.DB_MAX_OUTPUT_PORT_TYPE
out[2] <= reduce_or~4.DB_MAX_OUTPUT_PORT_TYPE
out[3] <= reduce_or~3.DB_MAX_OUTPUT_PORT_TYPE
out[4] <= reduce_or~2.DB_MAX_OUTPUT_PORT_TYPE
out[5] <= reduce_or~1.DB_MAX_OUTPUT_PORT_TYPE
out[6] <= reduce_or~0.DB_MAX_OUTPUT_PORT_TYPE
out[7] <= <GND>
datain[0] => Decoder~0.IN3
datain[1] => Decoder~0.IN2
datain[2] => Decoder~0.IN1
datain[3] => Decoder~0.IN0


|clkscan3|clkscan:inst7
clk => scan_en[8]~reg0.CLK
clk => scan_en[7]~reg0.CLK
clk => scan_en[6]~reg0.CLK
clk => scan_en[5]~reg0.CLK
clk => scan_en[4]~reg0.CLK
clk => scan_en[3]~reg0.CLK
clk => scan_en[2]~reg0.CLK
clk => scan_en[1]~reg0.CLK
clk => data[3]~reg0.CLK
clk => data[2]~reg0.CLK
clk => data[1]~reg0.CLK
clk => data[0]~reg0.CLK
clk => state~0.IN1
reset => scan_en[8]~reg0.ACLR
reset => scan_en[7]~reg0.ACLR
reset => scan_en[6]~reg0.ACLR
reset => scan_en[5]~reg0.ACLR
reset => scan_en[4]~reg0.ACLR
reset => scan_en[3]~reg0.ACLR
reset => scan_en[2]~reg0.ACLR
reset => scan_en[1]~reg0.PRESET
reset => data[3]~reg0.ACLR
reset => data[2]~reg0.ACLR
reset => data[1]~reg0.ACLR
reset => data[0]~reg0.ACLR
reset => state~1.IN1
scan_en[1] <= scan_en[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
scan_en[2] <= scan_en[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
scan_en[3] <= scan_en[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
scan_en[4] <= scan_en[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
scan_en[5] <= scan_en[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
scan_en[6] <= scan_en[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
scan_en[7] <= scan_en[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
scan_en[8] <= scan_en[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[0] <= data[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[1] <= data[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[2] <= data[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[3] <= data[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
second[0] => div~0.IN11
second[0] => mod~2.IN11
second[1] => div~0.IN10
second[1] => mod~2.IN10
second[2] => div~0.IN9
second[2] => mod~2.IN9
second[3] => div~0.IN8
second[3] => mod~2.IN8
second[4] => div~0.IN7
second[4] => mod~2.IN7
second[5] => div~0.IN6
second[5] => mod~2.IN6
second[6] => div~0.IN5
second[6] => mod~2.IN5
second[7] => div~0.IN4
second[7] => mod~2.IN4
minute[0] => mod~0.IN11
minute[0] => div~1.IN11
minute[1] => mod~0.IN10
minute[1] => div~1.IN10
minute[2] => mod~0.IN9
minute[2] => div~1.IN9
minute[3] => mod~0.IN8
minute[3] => div~1.IN8
minute[4] => mod~0.IN7
minute[4] => div~1.IN7
minute[5] => mod~0.IN6
minute[5] => div~1.IN6
minute[6] => mod~0.IN5
minute[6] => div~1.IN5
minute[7] => mod~0.IN4
minute[7] => div~1.IN4
hour[0] => mod~1.IN11
hour[0] => div~2.IN11
hour[1] => mod~1.IN10
hour[1] => div~2.IN10
hour[2] => mod~1.IN9
hour[2] => div~2.IN9
hour[3] => mod~1.IN8
hour[3] => div~2.IN8
hour[4] => mod~1.IN7
hour[4] => div~2.IN7
hour[5] => mod~1.IN6
hour[5] => div~2.IN6
hour[6] => mod~1.IN5
hour[6] => div~2.IN5
hour[7] => mod~1.IN4
hour[7] => div~2.IN4


|clkscan3|clkdiv1ms:inst1
clkin => count[14].CLK
clkin => count[13].CLK
clkin => count[12].CLK
clkin => count[11].CLK
clkin => count[10].CLK
clkin => count[9].CLK
clkin => count[8].CLK
clkin => count[7].CLK
clkin => count[6].CLK
clkin => count[5].CLK
clkin => count[4].CLK
clkin => count[3].CLK
clkin => count[2].CLK
clkin => count[1].CLK
clkin => count[0].CLK
clkin => clkout~reg0.CLK
clkout <= clkout~reg0.DB_MAX_OUTPUT_PORT_TYPE


|clkscan3|button:inst9
clk => cnt[5]~reg0.CLK
clk => cnt[4]~reg0.CLK
clk => cnt[3]~reg0.CLK
clk => cnt[2]~reg0.CLK
clk => cnt[1]~reg0.CLK
clk => cnt[0]~reg0.CLK
clk => signal~reg0.CLK
clk => enable~reg0.CLK
clk => cnt[6]~reg0.CLK
phn => always0~0.IN1
signal <= signal~reg0.DB_MAX_OUTPUT_PORT_TYPE
cnt[0] <= cnt[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cnt[1] <= cnt[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cnt[2] <= cnt[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cnt[3] <= cnt[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cnt[4] <= cnt[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cnt[5] <= cnt[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cnt[6] <= cnt[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
enable <= enable~reg0.DB_MAX_OUTPUT_PORT_TYPE


|clkscan3|timer:inst6
clk => sec[6]~reg0.CLK
clk => sec[5]~reg0.CLK
clk => sec[4]~reg0.CLK
clk => sec[3]~reg0.CLK
clk => sec[2]~reg0.CLK
clk => sec[1]~reg0.CLK
clk => sec[0]~reg0.CLK
clk => min_clk.CLK
clk => sec[7]~reg0.CLK
reset => sec[6]~reg0.ACLR
reset => sec[5]~reg0.ACLR
reset => sec[4]~reg0.ACLR
reset => sec[3]~reg0.ACLR
reset => sec[2]~reg0.ACLR
reset => sec[1]~reg0.ACLR
reset => sec[0]~reg0.ACLR
reset => min_clk.ACLR
reset => min[6]~reg0.ACLR
reset => sec[7]~reg0.ACLR
reset => min[5]~reg0.ACLR
reset => min[4]~reg0.ACLR
reset => min[3]~reg0.ACLR
reset => min[2]~reg0.ACLR
reset => min[1]~reg0.ACLR
reset => min[0]~reg0.ACLR
reset => min[7]~reg0.ACLR
reset => hour[6]~reg0.ACLR
reset => hour[5]~reg0.ACLR
reset => hour[4]~reg0.ACLR
reset => hour[3]~reg0.ACLR
reset => hour[2]~reg0.ACLR
reset => hour[1]~reg0.ACLR
reset => hour[0]~reg0.ACLR
reset => hour[7]~reg0.ACLR
reset => started.ACLR
reset => h_clk.ENA
reset => day~reg0.ENA
start => started.CLK
sec[0] <= sec[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sec[1] <= sec[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sec[2] <= sec[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sec[3] <= sec[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sec[4] <= sec[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sec[5] <= sec[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sec[6] <= sec[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sec[7] <= sec[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
min[0] <= min[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
min[1] <= min[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
min[2] <= min[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
min[3] <= min[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
min[4] <= min[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
min[5] <= min[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
min[6] <= min[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
min[7] <= min[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
hour[0] <= hour[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
hour[1] <= hour[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
hour[2] <= hour[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
hour[3] <= hour[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
hour[4] <= hour[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
hour[5] <= hour[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
hour[6] <= hour[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
hour[7] <= hour[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
day <= day~reg0.DB_MAX_OUTPUT_PORT_TYPE


|clkscan3|clkdiv:inst
clkin => count[22].CLK
clkin => count[21].CLK
clkin => count[20].CLK
clkin => count[19].CLK
clkin => count[18].CLK
clkin => count[17].CLK
clkin => count[16].CLK
clkin => count[15].CLK
clkin => count[14].CLK
clkin => count[13].CLK
clkin => count[12].CLK
clkin => count[11].CLK
clkin => count[10].CLK
clkin => count[9].CLK
clkin => count[8].CLK
clkin => count[7].CLK
clkin => count[6].CLK
clkin => count[5].CLK
clkin => count[4].CLK
clkin => count[3].CLK
clkin => count[2].CLK
clkin => count[1].CLK
clkin => count[0].CLK
clkin => clkout~reg0.CLK
clkout <= clkout~reg0.DB_MAX_OUTPUT_PORT_TYPE


|clkscan3|button:inst5
clk => cnt[5]~reg0.CLK
clk => cnt[4]~reg0.CLK
clk => cnt[3]~reg0.CLK
clk => cnt[2]~reg0.CLK
clk => cnt[1]~reg0.CLK
clk => cnt[0]~reg0.CLK
clk => signal~reg0.CLK
clk => enable~reg0.CLK
clk => cnt[6]~reg0.CLK
phn => always0~0.IN1
signal <= signal~reg0.DB_MAX_OUTPUT_PORT_TYPE
cnt[0] <= cnt[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cnt[1] <= cnt[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cnt[2] <= cnt[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cnt[3] <= cnt[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cnt[4] <= cnt[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cnt[5] <= cnt[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cnt[6] <= cnt[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
enable <= enable~reg0.DB_MAX_OUTPUT_PORT_TYPE