clkscan3.map.eqn

采用Quartus2编写的数码管扫描显示电路 共有三个电路 电路1：当按下启动计时按钮时

--S21L5 is clkscan:inst7|lpm_divide:div_rtl_5|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~80
--operation mode is arithmetic

S21L5 = CARRY(!S21L7 & (M3L12 # M3L02));


--S7L7 is clkscan:inst7|lpm_divide:div_rtl_3|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~51
--operation mode is arithmetic

S7L7_carry_eqn = S7L01;
S7L7 = S7L7_carry_eqn $ (!M2L61 & !M2L51);

--S7L8 is clkscan:inst7|lpm_divide:div_rtl_3|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~53
--operation mode is arithmetic

S7L8 = CARRY(!S7L01 & (M2L61 # M2L51));


--E1_min[4] is timer:inst6|min[4]
--operation mode is arithmetic

E1_min[4]_lut_out = E1L92;
E1_min[4] = DFFEAS(E1_min[4]_lut_out, E1_min_clk, D2_signal, , , , , !E1L15, );

--S5L1 is clkscan:inst7|lpm_divide:div_rtl_3|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_4|add_sub_cella[1]~COUT
--operation mode is arithmetic

S5L1 = CARRY(E1_min[4]);


--M2L61 is clkscan:inst7|lpm_divide:div_rtl_3|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|StageOut[27]~525
--operation mode is normal

M2L61 = !S6L4 & (S5L2 $ E1_min[4]);


--S6L7 is clkscan:inst7|lpm_divide:div_rtl_3|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~51
--operation mode is arithmetic

S6L7_carry_eqn = S6L21;
S6L7 = S6L7_carry_eqn $ (!M2L7 & !M2L8);

--S6L8 is clkscan:inst7|lpm_divide:div_rtl_3|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~53
--operation mode is arithmetic

S6L8 = CARRY(!M2L7 & !M2L8 & !S6L21);


--M2L51 is clkscan:inst7|lpm_divide:div_rtl_3|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|StageOut[27]~27
--operation mode is normal

M2L51 = S6L4 & S6L7;


--M2L22 is clkscan:inst7|lpm_divide:div_rtl_3|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|StageOut[33]~526
--operation mode is normal

M2L22 = S7L4 & S7L7 # !S7L4 & (M2L61 # M2L51);


--S8L5 is clkscan:inst7|lpm_divide:div_rtl_3|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~80
--operation mode is arithmetic

S8L5 = CARRY(!S8L7 & (M2L12 # M2L02));


--E1L55 is timer:inst6|reduce_nor~142
--operation mode is normal

E1L55 = !E1_min[1] # !E1_min[0];


--E1_min[7] is timer:inst6|min[7]
--operation mode is normal

E1_min[7]_lut_out = E1L11;
E1_min[7] = DFFEAS(E1_min[7]_lut_out, E1_min_clk, D2_signal, , , , , , );


--E1_min[6] is timer:inst6|min[6]
--operation mode is normal

E1_min[6]_lut_out = E1L21;
E1_min[6] = DFFEAS(E1_min[6]_lut_out, E1_min_clk, D2_signal, , , , , , );


--E1_min[5] is timer:inst6|min[5]
--operation mode is arithmetic

E1_min[5]_lut_out = E1L32;
E1_min[5] = DFFEAS(E1_min[5]_lut_out, E1_min_clk, D2_signal, , , , , !E1L15, );

--R2L1 is clkscan:inst7|lpm_divide:div_rtl_3|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_ne8:add_sub_3|add_sub_cella[1]~COUT
--operation mode is arithmetic

R2L1 = CARRY(E1_min[5]);


--E1L65 is timer:inst6|reduce_nor~143
--operation mode is normal

E1L65 = E1_min[7] # E1_min[6] # !E1_min[5] # !E1_min[4];


--E1L15 is timer:inst6|reduce_nor~1
--operation mode is normal

E1L15 = E1_min[2] # E1L55 # E1L65 # !E1_min[3];


--C1L1 is clkdiv1ms:inst1|add~226
--operation mode is arithmetic

C1L1_carry_eqn = C1L4;
C1L1 = C1_count[13] $ (C1L1_carry_eqn);

--C1L2 is clkdiv1ms:inst1|add~228
--operation mode is arithmetic

C1L2 = CARRY(!C1L4 # !C1_count[13]);


--C1L3 is clkdiv1ms:inst1|add~231
--operation mode is arithmetic

C1L3_carry_eqn = C1L7;
C1L3 = C1_count[12] $ (!C1L3_carry_eqn);

--C1L4 is clkdiv1ms:inst1|add~233
--operation mode is arithmetic

C1L4 = CARRY(C1_count[12] & (!C1L7));


--C1L5 is clkdiv1ms:inst1|add~236
--operation mode is normal

C1L5_carry_eqn = C1L2;
C1L5 = C1_count[14] $ (!C1L5_carry_eqn);


--C1L6 is clkdiv1ms:inst1|add~241
--operation mode is arithmetic

C1L6_carry_eqn = C1L31;
C1L6 = C1_count[11] $ (C1L6_carry_eqn);

--C1L7 is clkdiv1ms:inst1|add~243
--operation mode is arithmetic

C1L7 = CARRY(!C1L31 # !C1_count[11]);


--C1L8 is clkdiv1ms:inst1|add~246
--operation mode is arithmetic

C1L8_carry_eqn = C1L11;
C1L8 = C1_count[8] $ (!C1L8_carry_eqn);

--C1L9 is clkdiv1ms:inst1|add~248
--operation mode is arithmetic

C1L9 = CARRY(C1_count[8] & (!C1L11));


--C1L01 is clkdiv1ms:inst1|add~251
--operation mode is arithmetic

C1L01_carry_eqn = C1L71;
C1L01 = C1_count[7] $ (C1L01_carry_eqn);

--C1L11 is clkdiv1ms:inst1|add~253
--operation mode is arithmetic

C1L11 = CARRY(!C1L71 # !C1_count[7]);


--C1L21 is clkdiv1ms:inst1|add~256
--operation mode is arithmetic

C1L21_carry_eqn = C1L51;
C1L21 = C1_count[10] $ (!C1L21_carry_eqn);

--C1L31 is clkdiv1ms:inst1|add~258
--operation mode is arithmetic

C1L31 = CARRY(C1_count[10] & (!C1L51));


--C1L41 is clkdiv1ms:inst1|add~261
--operation mode is arithmetic

C1L41_carry_eqn = C1L9;
C1L41 = C1_count[9] $ (C1L41_carry_eqn);

--C1L51 is clkdiv1ms:inst1|add~263
--operation mode is arithmetic

C1L51 = CARRY(!C1L9 # !C1_count[9]);


--C1L61 is clkdiv1ms:inst1|add~266
--operation mode is arithmetic

C1L61_carry_eqn = C1L32;
C1L61 = C1_count[6] $ (!C1L61_carry_eqn);

--C1L71 is clkdiv1ms:inst1|add~268
--operation mode is arithmetic

C1L71 = CARRY(C1_count[6] & (!C1L32));


--C1L81 is clkdiv1ms:inst1|add~271
--operation mode is arithmetic

C1L81_carry_eqn = C1L12;
C1L81 = C1_count[4] $ (!C1L81_carry_eqn);

--C1L91 is clkdiv1ms:inst1|add~273
--operation mode is arithmetic

C1L91 = CARRY(C1_count[4] & (!C1L12));


--C1L02 is clkdiv1ms:inst1|add~276
--operation mode is arithmetic

C1L02_carry_eqn = C1L52;
C1L02 = C1_count[3] $ (C1L02_carry_eqn);

--C1L12 is clkdiv1ms:inst1|add~278
--operation mode is arithmetic

C1L12 = CARRY(!C1L52 # !C1_count[3]);


--C1L22 is clkdiv1ms:inst1|add~281
--operation mode is arithmetic

C1L22_carry_eqn = C1L91;
C1L22 = C1_count[5] $ (C1L22_carry_eqn);

--C1L32 is clkdiv1ms:inst1|add~283
--operation mode is arithmetic

C1L32 = CARRY(!C1L91 # !C1_count[5]);


--C1L42 is clkdiv1ms:inst1|add~286
--operation mode is arithmetic

C1L42_carry_eqn = C1L72;
C1L42 = C1_count[2] $ (!C1L42_carry_eqn);

--C1L52 is clkdiv1ms:inst1|add~288
--operation mode is arithmetic

C1L52 = CARRY(C1_count[2] & (!C1L72));


--C1L62 is clkdiv1ms:inst1|add~291
--operation mode is arithmetic

C1L62_carry_eqn = C1L92;
C1L62 = C1_count[1] $ (C1L62_carry_eqn);

--C1L72 is clkdiv1ms:inst1|add~293
--operation mode is arithmetic

C1L72 = CARRY(!C1L92 # !C1_count[1]);


--C1L82 is clkdiv1ms:inst1|add~296
--operation mode is arithmetic

C1L82 = !C1_count[0];

--C1L92 is clkdiv1ms:inst1|add~298
--operation mode is arithmetic

C1L92 = CARRY(C1_count[0]);


--D2L12 is button:inst9|always0~0
--operation mode is normal

D2L12 = !reset # !D2_signal;


--S12L4 is clkscan:inst7|lpm_divide:mod_rtl_4|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_4|add_sub_cella[2]~41
--operation mode is normal

S12L4_carry_eqn = S12L01;
S12L4 = !S12L4_carry_eqn;


--S12_add_sub_cella[1] is clkscan:inst7|lpm_divide:mod_rtl_4|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_4|add_sub_cella[1]
--operation mode is arithmetic

S12_add_sub_cella[1] = E1_min[4];

--S12L3 is clkscan:inst7|lpm_divide:mod_rtl_4|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_4|add_sub_cella[1]~COUT
--operation mode is arithmetic

S12L3 = CARRY(E1_min[4]);


--M6L61 is clkscan:inst7|lpm_divide:mod_rtl_4|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|StageOut[27]~610
--operation mode is normal

M6L61 = !S22L2 & (S12L4 & (!S12_add_sub_cella[1]) # !S12L4 & E1_min[4]);


--S22L5 is clkscan:inst7|lpm_divide:mod_rtl_4|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~51
--operation mode is arithmetic

S22L5_carry_eqn = S22L01;
S22L5 = S22L5_carry_eqn $ (!M6L7 & !M6L8);

--S22L6 is clkscan:inst7|lpm_divide:mod_rtl_4|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~53
--operation mode is arithmetic

S22L6 = CARRY(!M6L7 & !M6L8 & !S22L01);


--M6L42 is clkscan:inst7|lpm_divide:mod_rtl_4|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|StageOut[33]~611
--operation mode is normal

M6L42 = !S32L2 & (M6L61 # S22L2 & S22L5);


--S32L9 is clkscan:inst7|lpm_divide:mod_rtl_4|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~61
--operation mode is arithmetic

S32L9_carry_eqn = S32L4;
S32L9 = S32L9_carry_eqn $ (!M6L61 & !M6L51);

--S32L01 is clkscan:inst7|lpm_divide:mod_rtl_4|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~63
--operation mode is arithmetic

S32L01 = CARRY(!S32L4 & (M6L61 # M6L51));


--M6L32 is clkscan:inst7|lpm_divide:mod_rtl_4|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|StageOut[33]~16
--operation mode is normal

M6L32 = S32L2 & S32L9;


--E1L5 is timer:inst6|add~389
--operation mode is arithmetic

E1L5_carry_eqn = E1L2;
E1L5 = E1_min[1] $ (E1L5_carry_eqn);

--E1L6 is timer:inst6|add~391
--operation mode is arithmetic

E1L6 = CARRY(!E1L2 # !E1_min[1]);


--R1L2 is clkscan:inst7|lpm_divide:div_rtl_1|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_ne8:add_sub_3|add_sub_cella[2]~32
--operation mode is normal

R1L2_carry_eqn = R1L6;
R1L2 = R1L2_carry_eqn;


--E1_hour[5] is timer:inst6|hour[5]
--operation mode is arithmetic

E1_hour[5]_lut_out = E1L52;
E1_hour[5] = DFFEAS(E1_hour[5]_lut_out, E1_h_clk, D2_signal, , , , , , );

--R1L1 is clkscan:inst7|lpm_divide:div_rtl_1|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_ne8:add_sub_3|add_sub_cella[1]~COUT
--operation mode is arithmetic

R1L1 = CARRY(E1_hour[5]);


--M1L01 is clkscan:inst7|lpm_divide:div_rtl_1|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|StageOut[22]~527
--operation mode is normal

M1L01 = !S1L2 & (R1L2 $ E1_hour[5]);


--S1L5 is clkscan:inst7|lpm_divide:div_rtl_1|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_4|add_sub_cella[2]~51
--operation mode is arithmetic

S1L5_carry_eqn = S1L01;
S1L5 = S1L5_carry_eqn $ (!M1L1 & !M1L2);

--S1L6 is clkscan:inst7|lpm_divide:div_rtl_1|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_4|add_sub_cella[2]~53
--operation mode is arithmetic

S1L6 = CARRY(!M1L1 & !M1L2 & !S1L01);


--M1L81 is clkscan:inst7|lpm_divide:div_rtl_1|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|StageOut[28]~528
--operation mode is normal

M1L81 = !S2L4 & (M1L01 # S1L2 & S1L5);


--S2L9 is clkscan:inst7|lpm_divide:div_rtl_1|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~56
--operation mode is arithmetic

S2L9_carry_eqn = S2L8;
S2L9 = S2L9_carry_eqn $ (!M1L01 & !M1L9);

--S2L01 is clkscan:inst7|lpm_divide:div_rtl_1|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~58
--operation mode is arithmetic

S2L01 = CARRY(!S2L8 & (M1L01 # M1L9));


--M1L71 is clkscan:inst7|lpm_divide:div_rtl_1|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|StageOut[28]~26
--operation mode is normal

M1L71 = S2L4 & S2L9;


--S31L4 is clkscan:inst7|lpm_divide:mod_rtl_0|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_4|add_sub_cella[2]~41
--operation mode is normal

S31L4_carry_eqn = S31L01;
S31L4 = !S3